ElectroTricks

🔸 What is Inrush Current? Inrush current is the large transient current drawn when a power-gated domain is turned ON. When a previously OFF domain is powered up: Its internal nodes are at 0V (or discharged state) Suddenly connected to VDD 👉 This creates a strong current surge to charge: Internal capacitances Interconnects Cell nodes 💡 Simple Understanding Turning ON a gated block =…

🔸 What is Electrostatic Discharge (ESD)? Electrostatic Discharge (ESD) is the sudden flow of charge between two objects with different electrical potentials, resulting in a high-current, short-duration pulse. In the context of VLSI, ESD events can occur during manufacturing, handling, packaging, or even normal operation, and can inject extremely high current into sensitive on-chip devices. From…

🔸 What is Electromigration? Electromigration (EM) is a reliability failure mechanism in integrated circuits caused by the gradual movement of metal atoms due to sustained current flow over time. At a physical level, when electrons flow through a conductor, they impart momentum to metal atoms (electron wind force), pushing them along the direction of current flow. Over time, this results in void…

🔸 Why Do We Need Dynamic IR Analysis? Static IR gives us:👉 Voltage drop due to average current But real chips don’t operate in averages. 👉 They operate in transitions (switching events) 💡 Key Limitation of Static IR Assumes constant current Ignores timing of switching Misses peak current events ⚡ What Dynamic IR Solves Dynamic IR captures: 👉 Instantaneous current during switching…

🔸 What is Static IR Drop? Static IR drop refers to: 👉 Voltage drop in the power grid due to average (DC) current consumption Unlike dynamic analysis: No time-varying switching No waveform-based behavior 👉 Each cell is assumed to draw a constant current 💡 Fundamental Relation Voltage drop is governed by: 👉 V = I × R Where: I → Average current drawn by cells R → Resistance of PG grid 🔸…

🔸 Why Do We Need Grid Check Analysis? Before running any IR drop analysis, one fundamental question must be answered: 👉 Is the power grid itself robust enough? If the grid is weak: IR drop analysis will fail anyway Debug becomes harder and time-consuming 💡 Key Insight Grid check is a pre-check for PDN health. It ensures: Uniform power delivery No weak connectivity No broken or…

🔸 Why Do We Need Special Low Power Cells? In modern SoCs: Multiple voltage domains exist Blocks can be powered OFF independently Signals cross between domains 👉 This creates challenges like: Voltage mismatch Floating signals Data loss As low power methodologies evolved, special cells like level shifters, isolation cells, and retention flops became essential for correct functionality. 🔹…

🔸 Why Power Gating Matters As technology scales into deep submicron nodes, power is no longer dominated only by switching activity. 👉 Leakage power has become a critical challenge In modern designs: Leakage increases exponentially with lower threshold voltages Even when blocks are idle, they continue to consume power As discussed in low-power methodologies, leakage in advanced nodes can…

🔸 Why PG Grid Design Matters In the previous post, we saw that PDN is the backbone of a chip. At the heart of PDN lies the Power Grid (PG Grid) — the on-chip network responsible for delivering power to every standard cell. 👉 A weak PG grid leads to: IR drop failures Electromigration issues Performance degradation 👉 A strong PG grid ensures: Stable voltage Reliable operation Timing…

🔸 The Real Problem: Power is No Longer Secondary Modern chip failures are rarely due to logic bugs. They are increasingly caused by power delivery issues. As technology scales: Power density keeps increasing Leakage current becomes significant Voltage margins keep shrinking This has made power a first-order design constraint in modern SoCs 👉 And this is exactly where PDN (Power Delivery…

Timing Delay Models – 2

Hi friends,

In the last post, we learnt Linear Model and NLDM for Timing delay modelling. Every timing model has a trade-off between accuracy and runtime. As we move to CCS and ECSM timing models, runtime in the evaluation of delay time increase.

So, Why CCS and ECSM? Why not NLDM? What was the limitation of NLDM?

There will be many such questions but there must be one more question that is – why…

TIMING DELAY MODELS – 1

Hi friends,

In the last couple of posts, we learned Interconnect Delay Models. As I told you earlier, we need to model delays for Driver, Receiver, and Interconnect, now we will learn to model Driver and Receiver delays.

The timing models are obtained after detailed simulations of the cell to model actual scenarios of cell operations. Timing models are specified for each timing arc of the cell.…

Interconnect Delays – 2

Hi friends,

In the last post, we learnt basic models of Interconnect Delays.  We learnt Ideal Wire, Lumped Model, and Lumped RC Model. Here is the tree network, which we were evaluating, in the last post.

Inspecting the tree, we can note that:

There is no resistance loop in the circuit.

All capacitors are connected between a node and ground.

There is only one input node in the circuit.

There is…

Interconnect Delay Models – 1

Hi friends,

While evaluating delays of paths in Static Timing Analysis, we check for setup and hold violations. These violations arise when data reaches the destination flop either too early or too late. That delay factor depends upon three important delays i.e. Driver Delay, Interconnect Delay and Receiver Delay. Modelling of these three delays is an important aspect for Static Timing Analysis.

SUMMARY – Setup and Hold Violations

Hi friends,

Link to the previous post.

In last many posts, we studied the basics of Static Timing Analysis and derived equations for removing setup and hold time violations in different circuits. In this post, we will summarize the methods of removing setup and hold violation. This post will not only include the information explained in the previous post but also adds new basic methods employed…

Li-Fi – Future of Wireless Technology

Picture this-you wake up and as you glare the dressing mirror, it speaks up the weather and hot news for you. You tap your smartphone to switch on your coffee machine. As you make breakfast, your refrigerator sends you text that you are out of drinks. Clued in with this message, your car’s GPS routes you to the shop on way back from office. You enter the parking and your car will start getting…

Hi friends,

Link to the previous post.

In the previous post, we discussed methods to check Setup and Hold Violations in different sequential circuits. We derived some general equations which helped us to evaluate constraints on different circuit’s timing elements. In this post, we will learn how to evaluate maximum clock frequency for a sequential circuit. Many people get confused by the term…