#distributed rc model

Interconnect Delays – 2

Hi friends,

In the last post, we learnt basic models of Interconnect Delays.  We learnt Ideal Wire, Lumped Model, and Lumped RC Model. Here is the tree network, which we were evaluating, in the last post.

Inspecting the tree, we can note that:

There is no resistance loop in the circuit.

All capacitors are connected between a node and ground.

There is only one input node in the circuit.

There is…

Interconnect Delay Models – 1

Hi friends,

While evaluating delays of paths in Static Timing Analysis, we check for setup and hold violations. These violations arise when data reaches the destination flop either too early or too late. That delay factor depends upon three important delays i.e. Driver Delay, Interconnect Delay and Receiver Delay. Modelling of these three delays is an important aspect for Static Timing Analysis.