#fpga

Super station one - Mister

Good news: I got a giant ass board that I can take home.

basically, the FPGA has a 12mhz clock input, and an adjustable clock output which goes to the CPU.

with the 12mhz FPGA clock, the CPU can run up to 6mhz. however, since the 6502 uses a synchronous bus, all the other devices on the bus must be able to run at that speed as well. and, well, they can't.

my solution was to dynamically adjust the clocking for each peripheral on the bus when it's being accessed. the FPGA monitors the address bus, and when the CPU selects something that runs slower, such as the EEPROM, it halts the clock for a little bit until the EEPROM can catch up.

this allows me to put other stuff on the bus too, like the LCD controller. in the original Ben Eater design, the LCD was attached through the VIA (essentially a GPIO controller). since the nature of the LCD controller needing to constantly switch between reading and writing, this made a pretty sizable overhead. by putting it on the bus directly, not only do we free up 7 GPIO pins, we also significantly reduce the time it takes for something to be written to the screen.

there's was problem though; I plan on using the VIA's timer functionality which essentially just counts clock cycles. if the clock constantly changes speed, this number will be useless. so, the FPGA generates two clocks, a monotonic clock for the VIA, and a non-monotonic clock for everything else.

but the VIA also needs to be synced with the CPU in order for them to communicate. so, when the FPGA sees that the CPU wants to access the VIA, it synchronizes their clocks for a short moment, then essentially "connects" them together for one cycle, before reverting to their original clocks.

this way, the VIA can properly keep time, and the CPU can change its speed at any time. additionally, since the VIA has its own clock, you can adjust it independently and slow it down if you need to track long periods of time, or speed it up if you need more precision.

You're still making the thing run on other, newer hardware. You're just not doing it in software. The FPGA is still just pretending very hard to be a SNES or what have you. The main difference is that there's not an entire operating system running underneath the emulator. It's not even running on the bare metal -- it is the bare metal, so there's a significant lack of overhead and with a good design input lag can be all but eliminated.

But it's still just an emulator.

After all, this

is not this

any more than this is

Delete any .cfg files.

Make sure that you have the latest version of the core.

Make sure that you have the latest version of N64-database.txt.

Make sure that you have the N64 BIOS. You can get the BIOS from the MAME 0.260 non-merged ROMset. The BIOS is the .bin file in the .zip file of your choice.

Rename your choice of BIOS to boot.rom. (Remember to change the extension, not just the name.) Any additional BIOS would be renamed boot1.rom and boot2.rom if included.

Put the BIOS where the N64 core would be.

Place the BIOS in the folder where the N64 ROMS are if you are still having trouble.

Place the N64-database.txt file in the folder where the N64 ROMS are if you are still having trouble.

Locations of the BIOS files in the ROMset

The Nipponese BIOS is pifdata.bin in n64dd.zip.

The American BIOS is pifntsc.bin in n64.zip.

The European BIOS is pifpal.bin in n64_pal.zip.