#6502

BASIC bitch

ERIS6502 CPU基板 拡張ROM付 https://share.google/yMLRTlvrbSp0XJiLf

basically, the FPGA has a 12mhz clock input, and an adjustable clock output which goes to the CPU.

with the 12mhz FPGA clock, the CPU can run up to 6mhz. however, since the 6502 uses a synchronous bus, all the other devices on the bus must be able to run at that speed as well. and, well, they can't.

my solution was to dynamically adjust the clocking for each peripheral on the bus when it's being accessed. the FPGA monitors the address bus, and when the CPU selects something that runs slower, such as the EEPROM, it halts the clock for a little bit until the EEPROM can catch up.

this allows me to put other stuff on the bus too, like the LCD controller. in the original Ben Eater design, the LCD was attached through the VIA (essentially a GPIO controller). since the nature of the LCD controller needing to constantly switch between reading and writing, this made a pretty sizable overhead. by putting it on the bus directly, not only do we free up 7 GPIO pins, we also significantly reduce the time it takes for something to be written to the screen.

there's was problem though; I plan on using the VIA's timer functionality which essentially just counts clock cycles. if the clock constantly changes speed, this number will be useless. so, the FPGA generates two clocks, a monotonic clock for the VIA, and a non-monotonic clock for everything else.

but the VIA also needs to be synced with the CPU in order for them to communicate. so, when the FPGA sees that the CPU wants to access the VIA, it synchronizes their clocks for a short moment, then essentially "connects" them together for one cycle, before reverting to their original clocks.

this way, the VIA can properly keep time, and the CPU can change its speed at any time. additionally, since the VIA has its own clock, you can adjust it independently and slow it down if you need to track long periods of time, or speed it up if you need more precision.