#catqubits

Elevator Code News

Elevator Codes are a quantum error correction (QEC) innovation that reduces logical error rates by 10,000x with only a 3x increase in physical qubit overhead. This novel design by French-American company Alice & Bob uses a “concatenated” approach to prevent bit-flip faults, which prevent “scientific-grade” quantum computers.

Closing the “Scaling Gap”

The Scaling Gap is quantum computing's biggest challenge. Quantum systems are fragile and prone to two types of errors:

Bit-flips: When a logical "0" accidentally becomes a "1."

Phase-flips: Jumbled quantum phases in superpositions.

Alice and Bob's cat qubits feature "passive" hardware security that makes them resistant to bit-flips and have recently attained hour-long bit-flip lifetimes, but sophisticated algorithms require more. The current hardware cannot meet the required logical error rate of 10−9 (one error per billion operations) for FeMoco molecular simulation in chemistry applications with passive protection.

The “Floor and Sweep” Architecture of Elevator Codes

In place of Google and IBM's massive 2D grids (Surface Codes), the Elevator Code builds simpler structures like a Russian doll using concatenation.

Floors (Inner Code): The system handles phase-flips with 1D repetition codes. Buildings stack these like floors.

Elevator (Outer Code): One “logical ancilla” strip of qubits. It “sweeps” floors to check parity.

The elevator uses transversal CNOT operations to detect bit-flip defects across logical qubits as it goes through each floor. Recycling: After a check, the ancilla is measured, reset, and utilized for the next floor. A distinct ancilla for each check is eliminated by this “sweep-and-recycle” strategy, making the code more efficient.

Comparison between Efficiency and Performance

The Elevator Code handles the two error types differently to reduce hardware waste. Because cat qubits inhibit bit-flips at the hardware level, the Elevator Code may focus on phase-flips and use the “elevator” to clean up any remaining bit-flips.

Elevator Codes have a higher "rate," allowing them to pack more logical qubits into a smaller footprint than the Thin Surface Code or XZZX Code. Obtain a 10−12 high-fidelity error rate. Elevator Code requires 30% less qubits than Rectangular Surface Code (−12).

Why It Matters to Industry

According to standard architectures, a “scientific-grade” quantum computer with 100 high-fidelity logical qubits requires hundreds of thousands of physical qubits. Alice & Bob's simulation suggests utilizing Elevator Codes with 1,500 cat qubits. By using a linear, stackable architecture and decoupling error types, Alice & Bob have solved numerous 2D lattice connection constraints. This aids hardware fabrication and scaling.

Path to “Near Extinction” of Errors

Elevator Codes essentially “future-proof” cat qubits. Instead than waiting for new chip generations, it lets the company achieve ultra-low logical error rates on current technology.

Horizon Quantum and Alice & Bob Create Fault-Tolerant Computing again

Alice&Bob Company

Horizon Quantum Computing and Alice & Bob have partnered to bridge the gap between abstract quantum algorithms and robust, fault-tolerant hardware, advancing quantum utility. Horizon Quantum's “Triple Alpha” development environment and Alice & Bob's bespoke “cat qubit” emulators will be used in the partnership. The two companies seek to give developers a “full-stack” approach to constructing quantum-physics-resistant programs by combining Horizon's hardware-agnostic compilation with Alice & Bob's error-correction architecture.

The Noise Problem: Finding Fault Tolerance

Quantum computing has reached a turning point. Although “Noisy Intermediate-Scale Quantum” (NISQ) devices show promise for quantum speedup, decoherence—the tendency of quantum information to evaporate when disturbed by even the slightest heat or electromagnetic interference—plagues them. For banking, chemistry, and cryptography difficulties, industry must adopt Fault-Tolerant Quantum Computing (FTQC).

This shift requires Quantum Error Correction (QEC), which combines many physical qubits into a single “logical qubit” that is stable even if some of its pieces fail. However, typical QEC methods require millions of physical qubits to yield a few reliable logical ones. For years, this huge overhead has prohibited quantum computers from being economically viable.

The Efficiency Breakthrough of Alice & Bob

The “cat qubit” technology developed by Paris-based hardware pioneer Alice & Bob has garnered global notice. Unlike normal qubits, cat qubits include “built-in” safeguards against bit-flips, one of the two basic quantum blunders. Alice & Bob addresses one hardware problem, simplifying software error correction.

The company recently demonstrated that its architecture may reduce large-scale system physical qubit overhead by 200 times compared to standard superconducting approaches. The competitor's computer may only need 100,000 cat qubits to execute a task that requires 20 million physical qubits. This efficiency makes large-scale system realization easier.

Horizon Quantum: Quantum Stack Automation

Horizon Quantum Computing provides the “navigation system,” while Alice and Bob build the “engine.” Horizon, from Singapore, has been developing Triple Alpha for years. This software architecture automatically converts high-level code into efficient quantum circuits.

Horizon lets software engineers without PhDs in quantum physics use quantum computing. Their Triple Alpha platform lets programmers design device-independent apps and optimizes them for the hardware. Automation is needed to scale quantum applications outside labs.

Strategic Collaboration Details

The new agreement involves numerous important technology integrations to accelerate development:

Hardware Emulation on the Cloud: Alice & Bob will sell “virtual versions” of their forthcoming quantum processing units on Horizon's Triple Alpha platform. This lets programmers test their algorithms on cat-qubit hardware before the chips are deployed.

Horizon's advanced resource analysis capabilities will benefit Alice & Bob's backends. This lets developers track total qubit count, gate depth, and error rates at many abstraction levels. This knowledge is essential for "right-sizing" algorithms for early fault-tolerant computers.

Direct Compilation Pipeline: The deal makes Triple Alpha one of Alice & Bob's hardware compilation pipelines. Horizon's software will instantaneously apply advanced, error-corrected algorithms to Alice & Bob's next-generation QPUs.

Leadership Views on Future Rigor

Horizon Quantum Computing CEO Dr. Joe Fitzsimons said fault-tolerant systems are necessary to maximize quantum computing. By combining Alice & Bob's fault-tolerant hardware architectural expertise with Horizon Quantum's quantum programming and compilation expertise, he believes the collaboration will enhance fault-tolerant quantum computing.

Alice & Bob CEO Dr.”au Peronnin agreed, emphasizing the need for a research-based strategy. Peronnin added “building a complete quantum software stack requires careful integration of algorithms, error correction and compilation”. He believes Horizon Quantum can solve these issues.

Future: 2026 and Beyond

This relationship occurs as businesses grow rapidly. Horizon Quantum, based in Singapore, is the first software company to operate its own quantum computer. Additionally, the company is merging with dMY Squared Technology Group to pursue a Nasdaq public offering.

Meanwhile, Alice & Bob meet hardware plan goals. With over 150 employees and €130 million in investment, the company is ready to launch real-world hardware for difficult QEC operations.

The Cat Qubits are a quantum computing breakthrough that can be added to HPC processes. HPC SLURM News

Alice & Bob and Inria's “Unfolded Distillation” for Quantum Computing: A Comprehensive Look at Unfolding Magic

Inria and Alice & Bob researchers introduced “unfolded distillation” as a quantum computing method for creating “magic states”. This groundbreaking approach to universal fault-tolerant quantum computing is the most hardware-efficient method yet.

Magic States Are Essential to Quantum Computation

Universal quantum computation requires a quantum computer to handle all basic operations, or “gates,” so it can run any quantum algorithm, including those that outperform classical algorithms like Shor's and Grover's. Some of these gates need magic states, while others can be built easily. Essential magic states enable non-trivial actions that cannot be performed directly, completing the universal gate set for quantum computation. Without adequate state preparation, complex quantum algorithms cannot reach their full potential.

Magic State Preparation's Lasting Challenge

Magic states were once one of quantum computing's most resource-intensive tasks. Early ideal designs for magic state distillation required elaborate three-dimensional (3D) qubit arrangements, which presented substantial engineering challenges for solid-state quantum processing units (QPUs).

An unusual two-dimensional (2D) design could achieve magic states with low error rates with fewer qubits (463), according to current research, particularly from Google experts. This 2D technique advanced quantum error correction by overcoming 3D design obstacles and decades of research. The overhead remained a key hurdle to the development of practical quantum computers despite these advances.

Breakthrough of “Unfolded Distillation”

Like flattening a box, Alice & Bob and Inria researchers have ‘unfolded’ the theoretical 3D code into a more practical two-dimensional layout, building on and expanding past work. Because of its unique structure, this brilliant new method for preparing magic states is internally called the “Heart Code.”

This “unfolded distillation” technique reduces overhead and streamlines operations, making magic state preparation faster and cheaper in qubit requirements. One magic state requires only 53 qubits, demonstrating efficiency. This reduces qubit requirements 8.7-fold compared to state-of-the-art approaches. By using five times fewer quantum error correction cycles, it achieves the same high error rate of less than 1 in a million at five times the speed of current superconducting platforms.

The easy integration of this new magic state protocol into Alice & Bob's quantum error correcting architecture is a major gain. The method uses only the physical cat qubits in their setup and basic operations. No new developments are needed, so the business can focus on meeting performance targets.

Noise-Biased Cat Qubits Matter

Alice and Bob's cat qubits enabled this. The “noise bias” in these qubits precludes quantum computing bit flip errors. This particular feature significantly reduces hardware overhead for effective quantum computing. Another Alice & Bob investigation found that cat qubits' noise bias improves complicated error codes like LDPC in addition to magic state preparation. The “Heart Code” works best with noise-biased qubits.

Diego Ruiz, author of the paper and Ph.D. candidate at Alice & Bob and Inria, noted that quantum's most advanced players have lined up breakthrough after breakthrough to reduce magic state preparation costs, and it's exciting to see how it improves noise-biased qubits.

Enabling Practical Quantum Computers

This paper establishes the road to the universal fault-tolerant gate set needed to execute large-scale quantum applications and shows a significant technological gain in quantum hardware efficiency.

Cat-Transmon Hybrid Design

The California Institute of Technology and the AWS Centre for Quantum Computing have developed a new quantum computing architecture that will significantly reduce the hardware overhead required to build fault-tolerant quantum computers. This novel Hybrid Cat-Transmon Architecture concept uses “cat qubits” and “transmon qubits” to improve  quantum error correction  using existing, validated experimental methods.

Building reliable logical qubits from physically noisy components requires quantum error correction. QEC sometimes takes many physical qubits to produce a stable logical qubit, making it prohibitively expensive. The hybrid architecture, which reduces physical qubits, solves this problem immediately.

Utilising Biassed Noise for Efficiency

A key innovation of this design is its use of dissipative cat qubits as data qubits. The biassed noise of cat qubits makes them promising. Z-type errors are more likely than X-type errors (usually by a factor of 10³ to 10⁴) due to physical imperfections such photon loss and dephasing. One might purposely accelerate QEC by taking advantage of this large “noise bias”.

Using cat qubits to boost QEC efficiency was difficult, especially with “bias-preserving gates” (sometimes termed “cat-cat gates”) between cat qubits. These gates had “onerous experimental requirements” such strong planned dissipation and extremely good coherence. The hybrid approach successfully overcomes these obstacles by monitoring error syndromes with transmon qubits. It allows high-fidelity syndrome measurement and is more practical.

Innovative Gates for Complete Error Correction

The architecture controls suppressed X faults and dominating Z mistakes with two types of Hybrid Cat-Transmon Architecture entangling gates for complete scalability:

The cat qubit's transmon-controlled X operation, the CX Gate, fixes common Z errors. The qubits' natural free evolution under dispersive coupling makes its implementation easy. Operating the transmon with near "chi matching" in the |g⟩,|f⟩ manifold maintains a significant noise bias, while doing so in the |g⟩,|e⟩ manifold may reduce the cat's noise bias. Preventing single transmon decay faults from creating cat X mistakes makes it a “moderately noise biassed” gate.

CRX Gate: A new cat-controlled transmon X rotation that eliminates residual, suppressed X faults ensures the architecture's perfect scalability to arbitrarily low logical error. Unlike the exponentially noise-biased CX gate, the CRX gate's X-error suppression increases considerably with the cat's mean photon number. Composite pulse sequences of number-selective transmon pulses and storage mode drivers implement it.

This gate uses pulse shaping and dynamical decoupling to reduce coherence faults and dephasing. The CRX gate enables high-fidelity cat Z and controlled-Z (CZ) rotations and single-shot Z-basis cat readout with exponentially suppressed error.

CX and CRX gates are desirable because they leverage intrinsic dispersive coupling, require little planned dissipation, and don't require sophisticated Hamiltonian engineering.

Performance and Hardware Efficiency Potential

Numbers from the research predict significant performance gains. Cat-transmon gates have 99.9% fidelity and 200 ns speed. They maintain a considerable noise bias between 10³ and 10⁴. With realistic physical error rates of 10⁻³ and a storage mode loss rate to dispersive coupling (q) ratio between 10⁻⁵ and 10⁻⁴, current state-of-the-art coherence may attain this level of performance

Architecture uses thin rectangular surface codes to maximise biassed noise benefits. These algorithms reduce qubit overhead by protecting against Z mistakes more than X faults.

The cat-transmon approach reduces logical memory overhead far more than quantum architectures without biassed noise. Using current specifications, the cat-transmon architecture might achieve a logical memory error rate of less than 10⁻¹⁰ with merely 200 qubits (100 cat and 100 transmon). To match the overhead of the cat-transmon design, an unbiased-noise architecture needs over 1000 qubits or lowers physical error rates to less than 10⁻⁴.

Future View

The design is promising, but decoherence, notably of transmon qubits, limits its performance. Some devices have ultra-high intrinsic storage lifetimes (tens of milliseconds), but transmon lifespan must be improved to use them. More coherence enhancements are needed for 2D devices to reach deep sub-threshold.