New Bus.
I've finally finished adding my new bus interface to my wire-wrap PikaPC prototype.
It is … a mess. A made a point to run my wires more direct this time, rather than trying to keep them clean. I think part of the problem I was having with the ViRGE is some of my wires were longer than they needed to be and getting some interference from the neighboring wires they were bundled with. Shorter, straight-line wiring looks much worse, but should actually help with signal integrity.
I've also received my PCBs and the parts to assemble them. I even assembled the power supply & DRAM cards.
But if I already have the cards, why would I continue with tediously hand-wiring a 32-bit bus?
The prototype works as a base platform. It has ROM, RAM, and I/O; it boots to an interactive environment. That was its entire reason for existence to begin with — a platform for me to learn how to build hardware & software for PowerPC. My plan is to test and debug the new cards using the prototype to minimize the number of variables while debugging. Once the cards are working, I can pull them together on my backplane to complete the new system.
This approach also gives me the ability to debug the bus control logic for my new PPC403 host card. I copied the CPLD pinout from the new host card to the prototype, so once I have it working I'll be able to reuse the proven chip.
So that's my next step — writing the bus control logic in verilog. After that's working, next will be writing the corresponding control logic for the DRAM card.
