Jun 14
Ubuntu 26.10 entra nel vivo dello sviluppo con le prime Daily Build per desktop. Novità per RISC-V, GNOME 51 e integrazione AI locale. #Ubuntu #Linux #OpenSource #GNOME #RISCV
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Ubuntu 26.10 entra nel vivo dello sviluppo con le prime Daily Build per desktop. Novità per RISC-V, GNOME 51 e integrazione AI locale. #Ubuntu #Linux #OpenSource #GNOME #RISCV
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I really like RISC-V, but it looks like they keep putting NPU’s on the chips and marketing then as ai, but I think an open cpu that can run development software, etc. is more important right now, because not all RISC-V users are gonna be like OMG ITS AI I GOTTA GET THIS SBC!!!!
I saw a review of an sbc where 16GB of the 32GB was reserved for the NPU, and I think that’s bullshit
The collaboration will leverage CEA-List’s RISC-V design expertise and CEA-Leti’s silicon photonics expertise to introduce high-bandwidth
CEA-Leti, CEA-List, and PSMC have joined forces to integrate RISC-V architectures with microLED-enabled silicon photonics—unlocking high-bandwidth, energy-efficient data communication for future computing systems. By combining customizable RISC-V processing with optical interconnects and advanced 3D chip stacking, this collaboration aims to overcome the limitations of traditional copper interconnects and power constraints, paving the way for scalable, high-performance AI solutions.
T2M High-Performance RISC-V IP Platform for Intelligent Embedded Computing
T2M provides a high-performance RISC-V IP platform delivering silicon-proven 32-bit and 64-bit processors for scalable embedded and application-class system-on-chip designs. Supporting configurable RV32 and RV64 architectures, the portfolio enables implementation across a wide spectrum of power and performance requirements. Designed for smart IoT systems, automotive electronics, industrial automation, consumer devices, and AI-enabled edge platforms, the cores integrate superscalar execution, vector acceleration, crypto processing, DSP capabilities, and configurable floating-point support.
The architecture incorporates hardware Root-of-Trust, advanced protection features, and ISO 26262 compliant functional safety up to ASIL-B and ASIL-D. Memory subsystems include tightly integrated storage with ECC reliability, complemented by scalable interrupt control and high-bandwidth AXI/AHB interfaces for efficient SoC integration. Supported by complete IP, subsystem, and development tool ecosystems and validated through production silicon, T2M RISC-V processors provide a robust foundation for next-generation embedded and compute-intensive semiconductor systems.
T2M Configurable RISC-V CPU IP for Next-Generation Semiconductor Design
T2M’s configurable RISC-V CPU IP portfolio offers scalable processing architectures designed for advanced embedded and compute-intensive system-on-chip solutions. Supporting both 32-bit and 64-bit implementations, the portfolio enables designs ranging from ultra-efficient microcontrollers to application-class processors with configurable performance characteristics. Designed for automotive, industrial automation, consumer electronics, and intelligent edge computing, the architecture integrates high-efficiency pipelines, vector and cryptographic extensions, DSP processing, and precision floating-point units.Security and safety are integral to the architecture, featuring hardware Root-of-Trust, advanced system protection, and ISO 26262 compliant functional safety up to ASIL-D. Memory subsystems incorporate tightly coupled storage with ECC reliability, supported by scalable interrupt frameworks and high-performance AXI/AHB interfaces for streamlined SoC integration. Extracted from production silicon and supported by full software and hardware development infrastructure, T2M RISC-V IP cores provide a flexible and dependable platform for semiconductor innovation.
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T2M Scalable RISC-V Architecture for High-Reliability Embedded Platforms
T2M delivers a scalable RISC-V IP Core architecture designed to support both embedded efficiency and high-performance computing within modern system-on-chip environments. The portfolio includes silicon-proven 32-bit and 64-bit processors supporting configurable RV32 and RV64 implementations optimized for performance, power efficiency, and design flexibility. Engineered for smart connected systems including automotive, IoT, industrial control, consumer electronics, and AI edge devices, the cores integrate superscalar execution, vector processing, crypto acceleration, DSP functionality, and flexible floating-point computation.
Hardware-level security is implemented through integrated Root-of-Trust and advanced protection mechanisms, alongside ISO 26262 functional safety support up to ASIL-B and ASIL-D. Memory architectures provide tightly coupled storage with ECC-based reliability, supported by scalable interrupt handling and high-speed AXI/AHB system interfaces for seamless integration. With production-proven silicon foundations and complete development ecosystem support, T2M RISC-V cores enable reliable and efficient next-generation semiconductor platforms.
T2M Silicon-Proven RISC-V Processing Solutions for Embedded and Compute Systems
T2M’s silicon-proven RISC-V processing portfolio offers scalable 32-bit and 64-bit CPU IP designed to support a wide range of embedded and high-performance SoC applications. With support for both RV32 and RV64 instruction sets, the architecture enables flexible implementation from ultra-low-power control systems to application-class compute platforms. Designed for automotive, industrial, consumer electronics, and intelligent edge environments, the cores integrate advanced execution pipelines, vector and crypto extensions, DSP acceleration, and configurable floating-point processing for optimized computational efficiency.Comprehensive security is provided through hardware Root-of-Trust, system protection mechanisms, and ISO 26262 compliant functional safety up to ASIL-D. Memory subsystems feature tightly integrated storage with ECC protection and reliability controls, complemented by advanced interrupt management and high-bandwidth AXI/AHB connectivity for streamlined SoC deployment. Built on production-proven silicon and supported by complete IP integration, software tools, and hardware design services, T2M RISC-V solutions provide a robust platform for advanced semiconductor development.
T2M RISC-V IP Core Portfolio for Scalable Embedded and High-Performance SoCs
T2M’s RISC-V IP Core portfolio delivers silicon-proven 32-bit and 64-bit processors engineered for scalable embedded and high-performance system-on-chip designs. Optimized for applications ranging from ultra-low-power microcontrollers to A55-class compute platforms, the portfolio supports both RV32 and RV64 instruction sets with configurable architectures to meet diverse power, performance, and area requirements. Designed for smart IoT, automotive, industrial automation, consumer electronics, and AI edge systems, these cores integrate advanced features such as superscalar pipelines, vector and crypto acceleration, DSP capabilities, and configurable floating-point support.
Security is built into the architecture with hardware Root-of-Trust, advanced protection mechanisms, and functional safety support up to ASIL-B and ASIL-D with ISO 26262 compliance. Memory subsystems offer tightly integrated storage with ECC and reliability enhancements, while scalable interrupt handling and high-bandwidth AXI/AHB interfaces enable seamless SoC integration. Extracted from production-proven silicon and supported by complete IP, subsystem, software tools, and hardware design services, T2M RISC-V cores provide a robust and flexible foundation for next-generation embedded and compute-intensive semiconductor platforms.