#68030

A few months ago I built an I/O expansion board for my homebrew 68030 project with a 4-port serial card to go with it, and got BASIC running for four simultaneous users. It worked, but not as well as I had hoped. I wanted to be able to run two of those serial cards to support 8 total users, but it had proven unstable enough that with just the one card I had to slow down the whole system to 8MHz.

So I designed a new serial card.

I had previously been running this computer without any issues at 32MHz with a mezzanine card with FPU & IDE as well as a video card. The main board by itself can clear 56MHz. Having to go all the way down to 8MHz just didn't sit well with me. I want this machine to run as fast as possible for its 8 users.

I put extra time into reviewing worst-case timing for all components and graphing out how signals would propagate. The 16C554 quad UARTs I'm designing around are modern parts that can handle pretty fast bus speeds themselves — easily up to 50MHz with no wait states on the 68030 bus — assuming all the glue logic can get out of the way fast enough.

Signal propagation delays add up quickly.

My first draft schematic used discrete 74-series logic for chip selection, signal decoding, timing, etc. At slower bus speeds this wouldn't have been a problem. But I want this thing to run as fast as possible. By the time critical signals had made it through all those logic gates, I was looking at already being well into one wait state by the time the UART would see a 50MHz bus cycle begin.

I needed something faster. I was also running low on space on the board for all the components I needed. The obvious answer was programmable logic. I settled on the ATF22V10 as a good compromise of speed, size, availability, and programmability. It's available in DIP with gate delays down to 7ns. Where discrete gates were necessary, I selected the fastest parts I could. The final design I came up with showed a worst case timing that would only need one wait state at 50MHz and none for anything slower.

It ended up being a tight fit, but I was able to make it work on a 4-layer board within the same footprint of my main board, putting some components on the back side. (It may look like a bunch of empty space, but there's actually a lot going on running full RS232 with handshaking for 8 ports).

New problem. I had blown my budget for the project. As much as I love those stacked DE9 connectors, they're expensive. And there's no getting around the $10 pricetag for each of those quad UARTs. Even using parts on-hand where possible, I was looking at a hefty Mouser order.

[jbevren] suggested using ganged RJ45 connectors with the Cisco pinout instead of stacked DE9, to save space & cut costs. [Chartreuse] suggested buffering the TTL serial TX/RX signals to drive the LEDs that are frequently included on PCB-mount RJ45 connectors. Both great ideas. I was able to cut 20% off my parts order and add some nice diagnostic lights to the design.

Two weeks later, I received five new PCBs straight from China. I of course wasted no time setting into starting to assemble one.

I really set myself up for a challenge on this one. I learned to solder some 25 years ago and have done countless projects in that time. But I think this might be the most compact, most heavily populated, most surface mount board I've ever assembled myself. (There are 56 size 0805 (that's 2x1.2mm) capacitors alone!)

After a few hours soldering, I had enough assembled to test the first serial port. If the first port worked then the other three on that chip should work too, and there's a great chance the other chip would work as well.

And it did work! After some poking around with the oscilloscope to make sure nothing was amiss, I started up the computer and it ran just fine at 8MHz.

And at 16MHz.

And at 25MHz.

And at 32MHz.

And at 40MHz.

And almost at 50MHz!

Remember what I said about my timing graphs showing one wait state for 50MHz? The computer actually booted up and ran just fine at 50MHz. The problem was when I tried typing in a BASIC program certain letters were getting switched around, and try as I might, BASIC just refused to 'RQN' my program. It was pretty consistently losing bit 3, likely from that signal having to travel just a tiny bit farther than the others. A problem that will probably be resolved with an extra wait state.

Good enough for a first test! A few hours more and I finished assembling the card.

I did have some problems with cleaning up flux off the board, and I had to touch up a few weak solder joints, but so far everything seems to be working. I've updated my little multi-user kernel to run all 8 users from this new card and it's running stable at 40MHz.

I need to update my logic on the 22V10 to fix a bug in the wait state generator. I would love to see this thing actually running at 50MHz — a 25% overclock for the 40MHz CPU I am currently running. I also want to expand my little kernel program to add some new features like the ability to configure the console serial ports and maybe even load programs from disk.

I left off with my 68030 homebrew project having just finished assembling a new PCB that was 1:1 with my wire-wrap prototype.

It did not work.

In theory, it should have been as simple as transferring all the chips from the prototype to the PCB and starting it up. Reality is never so friendly as that.

It was failing in a familiar fashion, with errors coming swiftly after startup. It reminded me of a big problem I'd had with at the beginning, before I had properly implemented the chip select signals for RAM. But I had solved that problem a long time ago, how could it be back?

Turns out I had the chip select signals for RAM routed backwards. The RAM chip for the high 8 bits of the data bus was getting the enable signal for the low 8 bits, and so on.

I dug out the glue logic, changed those four pin assignments, and burned a new CPLD and ... nothing. Nothing worked. It was worse than I started and now it wouldn't even run when I reassembled the prototype.

Back in the box it went, for months.

I finally pulled it out recently and set out to get it running, starting with all new glue logic.

The original logic was all done in the Quartus schematic builder. At the time, it was too complex for my rudimentary VHDL skills. I've been learning Verilog and have built some successful projects with it that are far more complicated than this glue logic. So I started from scratch, rewrote all the logic fully synchronous in Verilog.

I started testing as small and basic as I could, stepping through each piece to confirm it worked before moving on. The logic responded appropriately to signals toggled manually. The CPU was able to free run with its data bus held low and the glue logic providing the termination signals. It was able to run code from ROM.

There were of course a few odd bugs here and there in the new glue logic, but in all it progressed fairly smoothly. I started writing some test programs to test the bus and make sure I got the chip select signals right this time.

With no RAM actually connected, it failed every test just as expected. Finally, it was time to add in the RAM.

RAM tests passed. I had a working computer again! Time to dust off the source code for the TSMON monitor program and Enhanced BASIC.

TSMON loaded and ran with few problems. Similar to my 68000 build, I wrote an expansion ROM for TSMON to load BASIC from ROM into RAM before running it.

So now I'm back where I was a couple years ago — I have a homebrew 68030 running BASIC.

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