#zig-zag coding

The fields of image and video encoding and compression have been put to a lot of stress with increase in the capacity of Integrated circuits. As technology shrinks, more and more transistors can be put into an I.C and thus the demand for higher resolution images and videos are coming up which need better encryption algorithms. The image and video processing algorithms are very compute intensive and with increase in resolution, the width of the compute elements like adders, etc. increase and this increase the power consumption of the device by several times. Approximate computing can reduce the power consumption as careful approximation does not affect the output quality of the image and video. Fixed levels approximation yield inconsistent quality output for different images and videos. In this project, we propose a dynamic approximation based image processing circuit. We implement an input based dynamically approximate reconfigurable adders and sub-tractors who can adjust their level of approximation dynamically by looking at the input thrown to them and thus, can trade-off between quality and power saving. We implement the code in Verilog HDL and verify the power by using the power estimator in Xilinx ISE tool. The simulation will be demonstrated in Modelsim software.