Bus Translation
Through the 1990s, home computers made a slow transition from 5 volt logic to 3.3 volt logic (and continued down from there). The PowerPC 403, introduced in 1994, is a good example of this transitionary period. The CPU core itself runs at 3.3V, but it supports both 3.3V and 5V logic.
Since 3.3V peripherals are more common today, my plan was to use this as an opportunity to start making that shift from 5V to 3.3V myself. My initial minimal functional build used 3.3V ROM and RAM. And my plan was to use an FPGA (3.3V I/O) for generating video and interfacing with an SD card (also 3.3V I/O).
Then I found some fun new old stock video chips on eBay, and a poll on Discord encouraged me to lean in hard with the S3 ViRGE — a 5V part. My 3.3V ROM & RAM are not going to appreciate the 5V signals coming from the data bus on the ViRGE, so I'll need some level-shifting bus transceivers. This will section off my data bus into a 3.3V bus and a 5V bus.
Being an embedded processor, PowerPC 403GA has a lot of nice features for making it easy to interface with peripheral chips. But I'll be using the ViRGE chip configured for VESA Local Bus — a bus that is pretty tightly coupled with the Intel 386/486 bus. Most control signals between the two should be compatible, but I will need some additional glue logic to handle the VLB Address Strobe & Ready signals as well as logic to enable the level-shifting bus transceivers. So ultimately I'll end up with the 3.3V PPC403 bus and something approximating the 5V VLB.
I have a spare ATF22V10C programmable logic device that should work well for the minimal glue logic I'll need to connect my 3.3V bus to my 5V bus. These Atmel PLDs are programmed with CUPL, a minimal logic description language I've only used once before on my Wrap030 8-port serial card. It's not terribly difficult, but does require some detailed knowledge of the inner workings of the PLD's logic cells (for instance, I had to rework my logic after realizing all registers share the same reset & preload signals).
I used logisim to help plan out what logic I needed. The Address Strobe generation was the trickiest part; I needed to make sure it would only be asserted for one clock cycle at the beginning of the bus transaction. After a few revisions, I had something that would compile without error. I even learned how to use WinSim, the PLD simulator companion to WinCUPL.
Everything looked right in the simulation, but there are some quirks in how active-low signals are handled in CUPL and in WinSim. I wasn't entirely sure I had gotten my signal polarity configured properly. Simulations are great, but sometimes nothing will quite beat hard testing with a row of switches and a small forest of LEDs.
At human testing speeds of sub-1Hz, everything looks to be working as expected!
With my bus translation logic sorted I can get back to wiring. I'm still waiting for some parts to ship before I can work on the video circuit, so I'm planning on starting with the keyboard controller. It only needs an 8-bit data bus, so it should let me test my bus translation without having to wire all 32 bits.
