#machxo

Lattice the MachXOs of Company non volatile in series can programming logical device many times (PLD) Used for responding to the request that those usually adopt application of CPLD and low volume FPGA optimally: Veneer logic, it is total lug, bus interface, at electric control and control logic,etc.. These devices integrate the functions of CPLD and FPGA on a form chip. MachXO PLD is applied to extensively those need common I/O to expand, the interface is bridged and in the application of the power up supervisory function, it, through offering embedded storing, built-in PLL, LVDS I/O, remote on-the-spot staging (TransFR technology) with high capacity and efficiency on the single device And the low power consumption dormancy mode improves the integrated level of the system. The MachXO PLD series products are used in low-density application, including consumption, car, communication, computer, industry and medical application,etc. extensively. MachXO main advantage Power up, has realized the accuracy control in system start-up in 1ms Do not need external storage equipment, reduce the overall cost of system High-efficient and low-cost data buffering Integrated ring management, reduce the systematic total cost There is much voltage in the interface, and accelerated the running speed of the key function The power consumption will be reduced to 100μ A to await the opportune moment Operate through the apparatus, can carry on the on-the-spot staging of remote MachXO key feature Nonvolatile, can be many times reconfigurated Instant power up within several microseconds Single chip, do not need external storage equipment Remarkable design safety, does not need bit stream to intercept Reconfiguration, because of logical SRAM in several milliseconds Control SRAM and nonvolatile memorizer through the usable procedure of JTAG port Support the backstage programming of the nonvolatile memorizer Dormancy mode Support the quiescent current up to 100 times to limit TransFR reconstructs (TFR) Carry on the logic staging of scene while running in the system High I/O number and high logic density 256 to 2280 LUT4s 73 to 271 I/O mouths, have extensive capsulation choices Support the density to move Unleaded / RoHS compatibility is capsulated Embedded and distributed memory SysMEMTM embedded RAM piece up to 27.6Kbits High distributed RAM up to 7.5Kbits Specialized FIFO control logic Flexible I/O dashpot But the programming system I/O dashpot supports many kinds of interface: LVCMOS 3.3/2.5/1.8/1.5/1.2 LVTTL PCI LVDS, Bus-LVDS, LVPECL, RSDS sysCLOCKTM PLL Each apparatus and two simulation PLL at most Multiplication of clock, cuts apart and phase drift The system level is supported IEEE standard is 1149.1 border scanning Board year Shaker The apparatus runs under 3.3V, 2.5V, 1.8V or 1.2V electric power supply Intrasystem programming of compatible IEEE1532 Mini MachXO develops the kit It is an easy using, low-cost platform that mini MachXO develops the kit, can accelerate the assessment of MachXO PLD. This kit contains MachXO LCMXO2280 component, 2Mbit SPI flashing memory and 1Mbit SRAM, temperature sensor, used in the expansion head in I2C and SPI interface and several LEDs and subscriber switch. Systematic on utilizing mini sheet of preloading which develops the kit, can test the interface of 8 LatticeMico8 microprocessors and I2C, SPI, UART and SRAM within several minutes. Then, you can utilize reference design source code design circuit downloaded free, and operate these devices within an hour. Developing the board also has USB passways, can carry on JTAG programming and debug with main PC. A pin head is offered to MachXO PLD each PIO interface and I2C total collinear thorough fare of year of board. Until the intersection of terminal station and procedure that run drive interface, can pay, control to circuit board with menu at host computer. More details, please have a look around: http://solution.eccn.com/d/SA402121990.html Fig. 1 MachXO Mini Evaluation Board outside drawing Fig. 2 Mini SOC block-diagram Fig. 3 MachXO Mini Evaluation Board block-diagram