Blue Pearl Software

If you have ever aspired to write out-of-this-world RTL, there’s never been a better time as satellites, spacecraft, landers, and rovers are increasingly using FPGAs and ASICs in their sub-systems. Some recent peer-reviews have highlighted poor coding techniques that have resulted in space-electronics failures, e.g. a $1M CubeSat becoming inoperable by getting trapped in a …

The Visual Verification Suite Is Now Available and Locally Supported by LeadingEdgeProvide Inc. SANTA CLARA, California – March29, 2018 – Blue Pearl Software, Inc. a leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced it has entered into an agreement with LeadingEdgeProvide of Seoul, South Korea, to provide RTL …

Visual Verification Suite Now Available in Japan from both NeXtream and FUJISOFT Inc. SANTA CLARA, California – March23, 2018 – Blue Pearl Software, Inc. a leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced it has entered into an agreement with NeXtream of YokohamaJapan, to provide RTL verification solutions …

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DVCon China is a technical conference in China targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits.

Personalized JumpStart Services Ensure Out-of-the Box Productivity for ASIC, FPGA and IP RTL Verification SANTA CLARA, California – January 24, 2017 – Blue Pearl Software, Inc., a leading provider of Electronic Design Automation (EDA) software for ASIC, FPGA and IP design verification, today announced JumpStart training and consulting services. The JumpStart solution is included with …

Visual Verification Suite 2017.1 Adds Built-in Support for Microsemi Radiation Tolerant Libraries and Extended Formal Analysis SANTA CLARA, California – March 20, 2017 – Blue Pearl Software, Inc., a leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite 2017.1. The release extends its leadership in RTL …

Visual Verification Suite 2017.2 Delivers Xilinx Tcl App for Vivado Design Suite Accelerating RTL Verification SANTA CLARA, California – July 25, 2017 – Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite 2017.2. The release extends Blue Pearl’s leadership in RTL …

Announcing Visual Verification Suite 2017.3 SANTA CLARA, California – Nov 8, 2017 – Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced immediate availability of the Visual Verification Suite 2017.3. The Visual Verification Suite provides an advanced integrated RTL debugging, constraint generation and clock …

Working with ASIC and particularly FPGA designers, I’m frequently asked if finding bugs using existing simulation or emulation tools is sufficient. The short answer is “Yes”,but it’s not always the most efficient. As design sizes increase but schedules do not expand to match, designers find themselves frustrated by spending too much time looking at simulation …

Topic: “Just Do It. Users Want Results, not Technology. Who Cares if a Structural Analysis Tools is Using Formal Verification?”

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“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when? Structured development methodology was …

We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is …

Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects in the latest Blue Pearl 2016.1 release. …

John Molyneux, COO & Senior VP Sales and Marketing, Blue Pearl Software Introduction Today’s FPGA designs are typically developed by assembling between 50 to 100 unique IP blocks to form a complete System on Chip (SoC) including embedded processors, high speed serial interfaces, analog, signal processing and control logic. These systems are large, complex and …