#verilog

Instead of mutex locks, we have arbiters to deal with shared resources (memory blocks)... and it's good to know my first wacky arbiter works!

designing my 4 bit integer simple color mapping to the LCD, I am still figuring out what is the mismatch causing the pixels to move.

Most people compare FPGA and ARM as if they are competitors. They are not. They solve completely different problems. 🔹 What is ARM? ARM is a processor architecture. It executes instructions one by one: Fetch Decode Execute This is called sequential computing. It’s flexible, efficient, and powers: Smartphones Embedded systems IoT devices 🔹 What is FPGA? FPGA stands for Field-Programmable…

All I need is to write the decode+decompress module, copy the NTT to vector multiplication to Inverse NTT scheme, and an compress+encode module for the final 256 bit message. And we are done. It will be about 6k logic elements (I tend to over estimate to give myself a wider margin :P) I can write it as a separate module and worry about encryption+decryption integration later.

It's not as much of a clusterfrick as encryption where a total of 1+k multiplications should be done. Only k number of multiplications :D slightly less data managing headache?

I went with the no serialization route and did not design a 8 bit output serialization module. (the accumulator have two RAM blocks and can output two 16 bit numbers at once) I did make a serialization module, but I realized it's up to that arbitrary specs (if the next module can accept 16*2 input, then that serialization is not necessary). So I just connect the accumulator outputs as they are.

and yeah, it's technically done. It's wack, it's bad, but it's done.

Welp I still need to write that paper :P