#synplicity

SYNPLICITY Company claim, introduce, can improve traditional ASIC and ASSP prove high performance verification solution of new generation of procedure by a wide margin a few days ago - -Confirma? Platform. This platform integrates the software and hardware tool with first-class industry together, exactly combine into the highly Integrated hardware and assist and verify the solution, can help the customer to solve various ASIC and ASSP met at present and in the future and verify the difficult problem. Confirma platform includes designing the industrywide standard tool divided into groups and realized for a plurality of FPGA - -Certify of Synplicity? Software; Adoption TotalRecall that Synplicity puts out newly? Identify of technology? Pro software (TotalRecall? Technology can be totally visual to designing offering in the course of testing) ; And the most flexible prototype board on the market at present - -Group is in HAPS (HARDI ASIC prototype design system) of FPGA Prototyping hardware.

ASIC and ASSP designer demands to further improve authentication technique, at the same time, with the introduction of the high density device of new generation, group designs in FPGA prototype as authentication technique at present and develops one of the most quick fields. But up until now, one's own solution integration designer, the difficulty in this respect is still relatively great. At present, the possible solution is that the designer needs to choose different software and hardware tools from different manufacturers, so as to ensure, can satisfied with the intersection of designer and concrete the intersection of verification and demand, at the same time for the intersection of interoperability and the intersection of setting-up and specialized workflow of tool. The intersection of Confirma and solution of Synplicity, the intersection of software and hardware and the intersection of tool and high integration, overall can run so as to the actual speeding, thus has raised group prototyping usability and efficiency to FPGA by a wide margin.

ASIC of Synplicity proves a senior director Juergen Jaeger points out the marketing of the products: "CONFIRMA platform enables designer to launch verification in different way. Users needn't go to think how to reduce the work capacity of verification again, so as to meet the design program requirement for the products, only need to consider what verification this is done more, the quality of revised design and products that so as. Synplicity is in the unique favorable position, can take the lead in offering all essential technology, give full play to the prototyping high-performance advantage to FPGA of group, guarantee that very high ASIC and ASSP verify the solution to offer a feasibility and efficiency, it is easy to implement and can run and debug the cipher scheme with the actual speed in the course of testing. Make so prototyping as to really make sure convenient and apt to usely in Confirma platform, and efficiency is very high. "

SYNPLICITY Company and comparable to fairy and thinking in the department and announcing a few days ago that further expanded the operating range of the joint working group of superhigh capacity, set foot in area reduce and power consumption reduce issue, devoted to, offer for 65 the intersection of FPGA and cipher scheme one-key type to design the procedure.

In more than one year, the close cooperation between two Company, has defined and implemented numerous brand-new solutions, in order to improve, have a match clever to think 65 Virtex as much as possible? -Result quality and efficiency of cipher scheme of the ultra-high security in 5 FPGA. Synplicity-XILINX joint working group announced and submitted the first achievement of it to May of 2006 - -Succeed in developing SmartCompile? Technology, this is that a kind of increment designs the procedure, can not merely be the highest to promote and operate 6 the amount of time of time, still can guarantee at the same time logic design does not change. Such from RTL to routing of overall arrangement workflow support increment design, in make little Xu to FPGA, needn't recompilate the whole device change, designer.

Devoted to improving and fruiting for quality and run time wholly by a wide margin on initial stage of joint working group of the superhigh capacity, guarantee even if can keep designing the result to be steady while revising increment to FPGA cipher scheme at the same time. The second stage of the joint working group will further advance the work in this respect, area and power consumption aiming at reducing 65 nanometers and even more advanced chip are required.

The whole goal of the joint working group is offering for the fact that the designer's ultra-high security is designed and connecting in the one-key type design procedure, guarantee that can finish designing the iteration many times every day. Support various application because of the ultra high capacity FPGA, so the joint working group will introduce design procedure and tool of many kinds of optimization, in order to meet the unique designing requirement of different devices.

The cheif technology officer McElvain of Synplicity Company points out: "We feel to design the achievement of constant improvement for increment deeply satisfied with to the first stage of joint working group. With the development of joint working group, we hope it can further solve FPGA to design and prove various difficult problems of the respect, include the question that our customer cares about most - -Reduce the area and reduce the power consumption. "

SYNPLICITY and XILINX announced a few days ago that further expanded the operating ranges of the joint working group of superhigh capacity, set foot in area reduce and power consumption reduce issue, devoted to, offer for 65 the intersection of FPGA and cipher scheme one-key type to design the procedure.

In more than one year, the close cooperation between two Company, has defined and implemented numerous brand-new solutions, in order to improve, have a match clever to think 65 Virtex as much as possible? -Result quality and efficiency of cipher scheme of the ultra-high security in 5 FPGA. Synplicity-Xilinx joint working group announced and submitted the first achievement of it to May of 2006 - -Succeed in developing SmartCompile? Technology, this is that a kind of increment designs the procedure, can not merely be the highest to promote and operate 6 the amount of time of time, still can guarantee at the same time logic design does not change. Such from RTL to routing of overall arrangement workflow support increment design, in make little Xu to FPGA, needn't recompilate the whole device change, designer.

Devoted to improving and fruiting for quality and run time wholly by a wide margin on initial stage of joint working group of the superhigh capacity, guarantee even if can keep designing the result to be steady while revising increment to FPGA cipher scheme at the same time. The second stage of the joint working group will further advance the work in this respect, area and power consumption aiming at reducing 65 nanometers and even more advanced chip are required.

The whole goal of the joint working group is offering for the fact that the designer's ultra-high security is designed and connecting in the one-key type design procedure, guarantee that can finish designing the iteration many times every day. Support various application because of the ultra high capacity FPGA, so the joint working group will introduce design procedure and tool of many kinds of optimization, in order to meet the unique designing requirement of different devices.

The cheif technology officer McElvain of Synplicity Company points out: "We feel to design the achievement of constant improvement for increment deeply satisfied with to the first stage of joint working group. With the development of joint working group, we hope it can further solve FPGA to design and prove various difficult problems of the respect, include the question that our customer cares about most - -Reduce the area and reduce the power consumption. "