Can improve design performance HDL programming style and skill
Through being familiar with the device framework, is chosen appropriate hardware platform and silicon dice characteristic, and through disposing the appropriate and of good performance implementation tool, designers can obtain higher design performance. However, in it is to write the efficient HDL code for the goal device if the numerous methods to improve design performance are easiest to ignore. Programming style and skill that this text discusses can improve design performance.
Use and reset the impact on characteristic
Which kind of system level choice is there such influence that is important can emerge to the characteristic, area and power as resetting and choosing. Some systematic framework teachers stipulate that must use the overall situation systematically asynchronously to reset. Adopt, have a match clever the intersection of FPGA and framework that think, use and type that reset exert an important influence to the intersection of code and characteristic.
All is comparable to fairy and think in FPGA framework at present, look-up table (LUT) The unit is just like logic, ROM/RAM or shift register (SRL or shift register LUT) It is the configurated like that. The synthesis tool can educe that adopts a certain structure according to RTL code. However, in order to use LUT as the shift register, can't describe the reset function in the code, because SRL does not have reset function. This means too the shift register code with reset function can't get realizing (needs a plurality of flip-flops and relevant routes between the shift registers) best ,But the code without reset function can obtain the fast and compact realization result (use SRL) .
Two the intersection of situation and impact on area and power these, obviously a little, but impact on characteristic does not very obvious. Generally speaking, the shift register adopting the flip-flop and producing will not become the critical path in the design, because the sequence route between the registers does not usually have sufficient length that become the most long route in the design. And resources (flip-flop and routing) Can consume about designs other have overall arrangementing more partial and routing to choose to exert a negative influence, therefore may cause and route in the route more longly.
Specialized multiplier and RAM module
The multiplier is usually used in DSP to design. Have a match clever FPGA that think include the intersection of multiplication and private resource in the framework, have application of multiplier in a lot of design. These multipliers offer other functions besides carrying out multiplication to operate. Similarly, no matter which kind of application in fact, each FPGA can use RAM not of uniform size to design.
Comparable to fairy and think of FPGA and include several pieces of RAM module, can use in the design as RAM, ROM, large-scale LUT even common logic. It can obtain compactness, have more high-performance design to use multiplier and RAM resource, but reset and choose the one with front, there is negative influence, depend on specifically what used reset the type. RAM and multiplier module only include resetting synchronously, so if the codes of these functions use asynchronously to reset writing, the register then in the module is unable to use. This impact on characteristic is very severe. For example, the whole pipeline type multiplier of Virtex-4 device is adopted asynchronously and reset while designing, the frequency is the highest can only reach 200MHz, and after making the code into resetting synchronously, the characteristic can be raised by more than twice, frequency reachable 500MHz.
Treat the problem related to RAM from two respects. Similar to multiplier, Virtex-4 piece RAM has available output registers, uses the clock that they can reduce RAM to output time, improve the whole design speed. But register these offer, reset synchronously only, offer asynchronous to reset, so register in the contemporary yard adopt asynchronous to reset while describing right away unable to use these register.
When the second question comes from RAM and is used as LUT or common logic. The consideration based on area and characteristic sometimes, it is very beneficial to configure a plurality of logical LUT to ROM or common and compress and enter the single piece RAM. This through presuming the structure manually, or realize by mapping some logic design to RAM storage area not in use by automatic way. Because RAM synchronous reset function, resets(or not reset) synchronously as using When, can realize common that logical that shine upon without changing the design function that has been already defined. But reset it while describing as adopting asynchronously, this can not be realized.
Asynchronous will exert an influence on the common logic structure too to reset. If you can't have a match clever, think to because that all FPGA general-purpose register reset /set programming as abilities synchronous asynchronous, so the designer may think that it is nothing improper to use asynchronously and is restored to the throne. But this kind of assumption is usually Improper. If asynchronous to reset without being used,then set /can put as synchronous logic to last logic. In this case, can release extra resources and is used in logic to optimize.
In order to understand better asynchronously that resets how to influence optimizing the result, let's see the following some code examples not so ideal:
elsif (CLK'event and CLK = '1') then
always @ (posedge CLK, posedge RST)
In order to realize these codes, the synthesis tool can only be the data routing two LUTs, because 5 signals are correlated with realizing above-mentioned logic functions altogether. Realization scheme of a kind of possibility of the above-mentioned code.