To OC8051IP nuclear modification and test on FPGA
At the beginning of the eighties of the 20th century, Intel Company introduced MCS-51 one-chip computer, Intel released 8051 kernels to a lot of semi-conductive producers in the form of patent transfer subsequently, thus a lot of and compatible products of MCS-51 system appear. These products are the same as system architecture of MCS-51, adopt the cmos process, therefore daily series 80C51 come to designate all one-chip computers with 8051 command systems. In series 80C51, OC8051 is clear with the framework, fetch and mean bringing spacious, a great deal of higher advantages of clock efficiency and is favored by insider. This text provides a kind of simulator debug scheme on the basis of analyzing a OC8051IP kernel that OpenCores websites offered; Use, this scheme, has pointed out several logic errors among them and revised it, IP nuclear FPGA downloads test after finishing after revising finally.
1 OC8051 structural analysis
OC8051 IP kernel that OpenCores websites offer is the same as 8051 system architectures. All 8051 compatible command systems of kernel of this IP, the internal resource includes: 8 CPUs, addressing capability reaches 2* 64K; ROM of 4 KB and RAM of the 128 bytes; Mouth of 4 8 I/ Os; 16 internal timing / counter; 5 interrupt sources and 2 pieces of interrupt priority level. Adopt its each module of Verilog language pair to describe. System main module and functional specification are set out in Table 1. The correspondent source document of different module is named after module name, for example the accumulator A correspondent source document is oc8051_acc. v.
Though the kernel of above-mentioned OC8051 IP declares all 8051 compatible command systems, it is not like this while carrying out actually. Such as while carrying out the identical code of 2 groups of functions that Table 2 lists, execution results received are different. Code 1 execution to, as 0 the intersection of outside and RAM, code 2 execution come out 5 the intersection of load and address for 4 the intersection of outside and RAM 5 the intersection of load and address in result. The reason to cause this kind of phenomenon is, oc8051_ext_addr_sel module disposed and delayed one clock cycle while writing the outside RAM address. If want OC8051 IP kernel to keep the same with standard 8051 system, must revise the similar logic error in the source document.
A simulator debug of 2 OC805 and revising
As to hardware design, artificial function to prove, design the consequential logic function accord with the original regulation, if design going wrong on this level, then the work of each level will be totally uncertain. Knowing by preceding paragraphs, the logic error that OC8051 IP kernel exists, so it is necessary to realize the mistake is found out and positioned through the artificial means, thus finish to the Improper modification of logic finally.
2. A simulator debug scheme
OC8051 simulator debug scheme. Its principle is: Write the test procedure in Keil software environment, compile and produce. And hex file injects it into command register of ROM. Testbench be produced to be responsible fored work OC8051 clock and control make to be can equisignal,can't and have OC8051 carried out there outputted until text is result of order at ROM /in files undulate. The developer, through comparing the text / result that the undulate file carries out the test procedure with Keil debugging tool, thus it is Improper to logic to realize finding out and alignment, and revise IP kernel source document.
What merits attention is, though Modelsim is powerful, can observe the change of the module signal of any level conveniently, but OC8051 IP complicated in nuclear structure and sequence, avoid unavoidable emulation still, because middle the intersection of signal and large inconvenience brought. So, can seek some and simplify the mechanism operated during simulator debug. Consider that relies on data register indicator DPTR and accumulator A, MOVX order can export the value of any register in the procedure execution in the outside RAM, and the value observed in the outside RAM is relatively easy, therefore a literary grace has used this kind of mechanism.
2. 2 revises the method specifically
(1)Oc805 1_ext_addr_sel module
Reading and writing the outside RAM address can be pointed out by DPTR, can be pointed out by Ri too, the main function of this module is to choose to read and write the outside RAM address. Finish to the dispositions of buff and state through select and write signal, thus finish to reading and writing the disposition on the outside RAM address addr_out. In the intersection of Modelsim and environment, carry out 1 o'clock such as code in the Table 1, find change of addz_out always than the intersection of DPTR and first clock cycle slowly, therefore it carry out, come out 5 the intersection of load and address for 0 the intersection of outside and RAM. Having adopted always process at the time of the reason disposing buff and state to cause this kind of phenomenon, this text changes these some codes into:
asstgn buff =" select" ? {8h00, ri} : {dptr_hi, dptr_lo} ;
This module is made up by one and 8 flag registers and control logic, is used for collecting relevant states after instruction execute. Every state of 8 bit registers usually takes shape automatically in instruction execute, but can be adopted the move instruction to change depending upon need by users. Responsible for explaining the logic of the move instruction adopts if sentence original design:
if(addr[7: 3]=='OC8051_SFR_B_ACC) data_out[addr[2: O]]
' OC8051_SFR_B_ACC is defined as 5 high bit addresses of the accumulator A, it is obviously wrong to use in here. Should change it into 5 high bit addresses of the program status word PSW ' OC8051_SFR_B_PSW.
