SPI stands for serial peripheral interface which is an interface bus that transmits data between microcontrollers and small peripherals including sensors, SD cards and shift registers. SPI was introduced by Motorola in the year 1979 and it is also referred to as four wire serial bus. There are similar protocols available such as Microwire developed by National Semiconductor. In a simpler sense, an SPI is a four-wire single ended serial communications interface found in many microprocessors/microcontrollers, peripheral chips which enables the controllers and peripheral devices to communicate with each other. Communication with two processors is also possible with an SPI though it was developed for the purpose of communication between a host processor and it’s peripherals. SPI can operate with single master and multi master protocols even though multi-master mode is rarely used.
Synchronous Transmission:
According to the nature of the signals used to synchronise the master and slave devices, data transmission protocols are classified into two. Sychronous data transmission and asynchronous data transmission. SPI is a synchronous data transmission protocol. In synchronous data transmission, the sender and receiver share a clock with one another. Otherwise, the sender provides a timing signal which prompts the receiver to read the next bit of the data. During data transmission, if there is no data available to transmit at a given instant, a fill character will be sent to make sure that the data is always transmitted.
While in the case of asynchronous transmission, data should be transmitted without a clock signal being sent by the sender. In general case, the sender and receiver come in agreement with the speed of transmission. To make sure the data accessing follows that agreement, both the sender and the receiver set up their own internal circuits. In order to synchronise the sending and receiving units, special bits are added to each word.
Basic Connections and Data Control Lines of SPI:
Figure shows the control lines and data lines of a single master-single slave SPI. The signal wires are MOSI, MISO, SCLK and SS. A MOSI signal is generated by the master device and it is received by the slave whereas a MISO signal is generated by a slave and received by the master. SCLK is the serial clock signal which is transmitted by the master to synchronise data transfer between the master and the slave. SS is the slave select signal which is transmitted to the chip select pin of the slave. It is an active low signal. MOSI signal is also named as serial data in (SDI) and MISO signal is named as serial data out (SDO). MOSI and MISO are data lines while SCKL and SS are control lines.
The pins are used according to the purpose. In case a device does not require an input, SDI pin may not be required and if a device does not require a output, SDO pin may not be present. Similarly if the communication is limited to one slave, then the CS pin on the particular slave device is grounded. In case of multiple slave operation, an SS signal is sent from the master to each slave device.
Most of the time, the communication will be between a single master and multiple slaves. The master generates a clock signal and using the slave select pin, it activates the slave device it wants to communicate with. The clock signal is provided to all slave devices if they are not selected for the communication at a particular time.
As discussed earlier, the master device initiates the communication. To initiate communication, the master generates clock signal which is of a frequency equal to or less than the maximum frequency the slave devices support. The slave device with which the communication has to be started is selected by pulling the chip select pin of the particular slave to low state. The slave devices which are not selected by the slave select signal will reject the clock signal as well as the MOSI signal. These slaves won’t generate the MISO signals.
The slaves have tri-state outputs which go to high impedance state when the device is not selected. Chip-select pin of these devices without this tri-state outputs will not be activated and therefor they can not share the SPI bus with other devices.
The data transmission is done in a full-duplex transmission mode. The data is sent by the master on the MOSI line and the slave reads it from the same line. Then the slave device sends a bit on the MISO line and the master reads it from the same line.
There data being transmitted are stored in shift registers associated with the master and the slave. When the master shift register shifts out a value through the MOSI line, the slave shifts the data into it’s register. While shifting data, MSB is the first one to be shifted out. After exchanging the data, the slave devices share the value and does the necessary operation. After the data transmission is done, the master stops generating the clock and the slaves are being rejected.
Clock Polarity and Phase:
Clock polarity and phase are the parameters which determine the edges of the clock. Apart from the clock frequency, the master should also configure the clock polarity and phase.
Clock polarity will determine if the clock idles high or low, if it is 1 clock idles high and if 0 clock idles low. Clock phase determines when data is transmitted relative to the clock. It’s value also depends on clock polarity, both of these parameters creates different modes in SPI.
Based on the clock polarity and clock phase, there are four modes that can be used in an SPI protocol. If the clock phase is 0, the data is latched at the rising edge of the clock with polarity 0 and at the falling edge of the clock with polarity 1. If the phase of the clock is 1, data is latched at the falling edge of the clock with polarity 0 and rising edge with polarity 1.
Master-slave Configurations:
There are different ways in which the slaves can be attached to the master. Mainly there are two types of configurations commonly used. They are daisy chain configuration and parallel configuration.
Daisy Chain Configuration:
In cascaded or daisy chain configuration, the clock lines and chip select lines of all devices are connected together. The data from the master flows through each peripheral and returns to the master. The data output of the preceding slave devicee is attached to the data in of the next device. This will give a feel of a larger slave shift register. Only a single SS line is required by the master.
Daisy Chain Configuration
Independent Slave Configuration:
In independent slave configuration, the MISO line, MOSI lines and clock lines of all the devices are connected together. But the chip select pin of each peripheral is connected to separate slave select pins of the master.
Independent slave configuration
SPI is a widely used protocol, so it is included in most of the microcontroller families. Atmel 8051 family and some AVRs use SPI for programmer communication. Some of the other chips using SPI are listed below.
Flash memories and EEPROMs, e.g: Microchip SST25VF080
Real Time Clock chips, e.g: Maxim DS1347
Aanalog to Digital converters, e.g: Microchip MCP3008
Battery management ICs, e.g: TI BQ76PL536
TFT LCD display drivers, e.g: ILI9341
Supports multiple slave devices
Full duplex communication, transfer data in and out at the same time.
Significantly high data rates (in megabits/second) as compared to other serial communication stands, sometimes in megahertz range.
Simple protocol and easy to implement for single-master single-slave applications
Less complex circuitry and there is no need of external transceivers, so it is a very easy interfacing. It doesn’t care about physical interface specifications and voltage ranges.
Required number of pins are high as compared to other serial protocols
Absence of in-chip addressing, it needs separate chip select of each devices
SPI doesn’t have an acknowledgement mechanism, so devices cannot confirm data reception and device existence.
SPI doesn’t have a flow control mechanism and it should be handled manually
It is a short distance communication by default, though there are solutions for extending for long-distance communication
