How SECQAI Ltd Is Improved Cybersecurity With CHERI & PQC
SECQAI Ltd
Ultra-secure semiconductor solutions business SECQAI completed the tape-out of its SE01 “Q-Locked” CHERI ISA V9 Trusted Platform Module (TPM), a groundbreaking announcement that might change digital security. This achievement, made utilising TSMC's 22nm technology, marks a milestone in the commercialisation of scalable, memory-safe, quantum-resistant computers. Capability Hardware Enhanced RISC Instructions (CHERI) and Post-Quantum Cryptography (PQC), two of the most powerful security paradigms, are merged into a single deployable hardware primitive in SECQAI, laying the groundwork for hardware trust in digitisation.
The tape-out on TSMC's industry-leading 22nm process is a technological achievement and a sign of the design's readiness for mass production. This accessibility is crucial because widespread hardware-level adoption is essential to ensure the digital future, especially in critical national infrastructure (CNI) and new industries like AI infrastructure where data secrecy and computational integrity are crucial.
Dual-Security Revolution: Addressing Current and Future Threats
Cryptographic integrity and platform authenticity underpin cloud servers, financial systems, and consumer electronics in the digital economy. The TPM often performs these roles. The TPM is a crucial security primitive that ensures hardware platform integrity, cryptographic key generation and storage, and device authentication while maintaining its internal integrity.
Cryptographically-relevant quantum computers (CRQCs) pose an existential hazard, while memory-related assaults are a systemic issue. SECQAI's memory-hardened “Q-Locked” SE01 quantum-secure firewall addresses both. The company invented the “Q-Locked” series to fix the many memory weaknesses that allow daily cyberattacks. It also provided the hardware needed for large-scale PQC application.
Removing Memory Vulnerabilities using CHERI
Memory security has long plagued computing. Microsoft and other studies reveal that memory safety problems cause 70% of all known Common Vulnerabilities and Exposures. These vulnerabilities, including buffer overflows, use-after-free issues, and integer overflows, allow hackers to gain unauthorised access, run malicious code, and take over a system.
The solution requires a thorough hardware memory pointer management overhaul, not just software improvements. CHERI's groundbreaking solution is here.
CHERI, developed by the University of Cambridge Department of Computer Science and Technology in collaboration with SRI International, extends the widely used RISC-V Instruction Set Architecture.
CHERI embeds unforgeable hardware-enforced descriptors into memory references. A capability specifies a memory block's address and enforces fine-grained limitations on its size and allowed actions (read, write, execute).
The SECQAI Q-Locked TPM uses the commercially available CHERI ISA v9 to operate memory-safely. The hardware quickly stops code that exceeds memory constraints. This architectural resilience shifts the security paradigm from “detect and patch” to “secure by design,” rendering most software flaws irrelevant for TPM safety by dramatically decreasing the attack surface.
Hardware Acceleration with PQC Imperative Future-Proof Cryptography
SECQAI is preparing future devices while fortifying the current. Shor's and Grover's algorithms on quantum computers could break RSA and ECC, which protect web traffic and bitcoin transactions. The U.S. National Institute of Standards and Technology (NIST) requires Post-Quantum Cryptography (PQC), which is quantum-resistant.
The SE01 Q-Locked TPM is designed to accelerate hardware implementation of novel, computationally intensive PQC algorithms. FIPS 203, 204, and 205 list its NIST-approved PQC algorithms. CRYSTALS-Dilithium and CRYSTALS-Kyber are lattice-based digital signature and key encapsulation solutions. Quantum-resistant PQC algorithms are more computationally intensive than conventional ones.
SECQAI incorporates acceleration directly into the TPM hardware in high-speed systems like commercial servers and next-generation AI accelerators to ensure a smooth PQC transition without latency or power consumption issues.
Due to its FIPS 140-3 architecture, the chip meets the demanding cryptographic module standards of regulated businesses and governments worldwide.
Making Global Adoption Possible
This tape-out matters commercially and strategically. SECQAI's CHERI-enabled, PQC-accelerated TPM gives OEMs a scalable 22nm commercial foundry component. The ability to integrate advanced hardware security across their whole product line, from mass-market consumer gadgets to commercial systems, democratises it. The SE01 chip is designed to build confidence by verifying commercial servers and AI infrastructure before they boot.
Teamwork led to this breakthrough, according to SECQAI CEO Rahul Tyagi: “They are excited to have reached this significant milestone. They worked together with a large OEM to satisfy the pressing requirement for more secure chips. The relationship with TSMC and VCA IMEC enabled the debut of this groundbreaking technology. They want to work with the industry to build secure, memory-safe computation.
SECQAI's Q-Locked CHERI TPM, which addresses memory vulnerability and the quantum threat, was taped out, marking a milestone for safe computing. SECQAI helps OEMs future-proof their systems and devices with architectural defence and hardware-level PQC acceleration through CHERI, enabling reliable cloud services and AI.
