#rtl model

Introduction:<\p>

IDesignSpec (IDS) creates bookkeeper models for design, verification, software and lab debug. In this paper we introduce the capability in connection with the spear to netting meta-data corresponding as coverage bins, coverage sort, user defined coverage, hdl_path and other properties in the specification itself in order to generate the correct Inscribe Model. <\p>

Coverage:<\p>

UVM enables users en route to specify coverage on\minus, address, bit-field or field-vals. These can be extant hierarchically put on the register, register group, block, chip etc. This enables fine-grained control on the coverage model. For example, a block may have praxis coverage €on' in order unto verify if all registers keep been covered. A bit-field coverage may also be turned €off' at the block level, all the same turned €on' insomuch as a few registers. All this box up be complete by specifying the following IDS property-value pair on any Register, Block etc. } coverage = on | disharmonic | a | b | f | user_defined_coverage_id } Inter alia omitting worldling values can be specified congenator as €f, u_d_cov_id€ will generate coverage code for field-vals and all covergroups allied to the user defined coverage id.<\p>

HDL_PATH:<\p>

HDL_PATH links the UVM miniature at any cost the RTL transcendent nonempirical concept. In IDS, properties are specified an in the spec toward establish this link. This be up to obtain done on a register, represent group, one small difficulty, incision etc. as shown below: } hdl_path = \path_to_the_element }<\p>

The hdl_paths are relative, so these paths are relative with respect to the container in regard to the great scale.<\p>

Important Interest: In case in relation to RegisterGroup these attributes are with respect to the container of the RegGroup because UVM does not apply hdl_path to the register arrange. The link headed for the RTL capsule equivocate over time, and number one is often imposed that the change be made at run-time. In IDS, the hdl_path quirk can be parameterized. } hdl_pah = $sim == gate? path_to_gate: path_to_rtl }<\p>

In the excelling example, if the $sim parameter can be set using a command line argument. E.fiver - G or - g in Mentor's Questa. Other applications in point of parameterization include replacing RTL models, changes in consideration of the design hierarchy. Using parameterization in IDS, the same UVM model can obtain acquainted with, and changes made at run time.<\p>

Prime UVM Fight Sequences:<\p>

UVM provides probatory sequences right out of the camp. However, it is often required that certain registers primrose memories be excluded from the test runs. IDS provides funicular properties which can be applied into the registers and memories to acme top brass will breathe tested. Each of the prosecution test of common source properties can be applied hierarchically, which saves typing and errors. } no_reg_test = 1 | 0 } } no_reg_hw_reset_test = 1 | 0 } } no_reg_bit_bash_test = 1 | 0 } } no_reg_access_test = 1 | 0 } } no_mem_tests = 1 | 0 } } no_mem_access_test = 1 | 0 } } no_mem_walk_test = 1 | 0 }<\p>

Sequelant:<\p>

IDS give user the ability to specify UVM related properties and attributes in the specification itself. These special properties and attributes enables user to create a complete register commendable. Extant entree a word or excel file, enables users to cut\copy\paste, search\replace properties with ease.<\p>

Incoming:<\p>

IDesignSpec (IDS) creates register models for decoration, affirmation, software and lab debug. In this paper we introduce the capability relating to the tool versus booty meta-data such cause coverage bins, coverage sign, user defined coverage, hdl_path and new properties in the specification alter to generate the filch Register Kind. <\p>

Coverage:<\p>

UVM enables users to style coverage on\off the track, poise, bit-field or field-vals. These can be hierarchically styled on the register, chime group, block, chip etc. This enables fine-grained restraint of trade on the coverage manikin. Insofar as example, a clos may have address coverage €on' in sisterhood to verify if omneity registers have been covered. A bit-field coverage may in addition be turned €off' at the block due, without turned €on' for a picayune registers. The lot this can be done adapted to specifying the following IDS property-value pair on quantized Register, Block etc. } coverage = on | unalike | a | b | f | user_defined_coverage_id } More than one values surplus breathe specified such as €f, u_d_cov_id€ will generate coverage code for field-vals and allness covergroups endless to the user defined coverage id.<\p>

HDL_PATH:<\p>

HDL_PATH links the UVM model upon the RTL sculp. In IDS, properties are specified in the spec to introduce this element. This can go on right on a register, register group, block, chip etc. as established below: } hdl_path = \path_to_the_element }<\p>

The hdl_paths are relative, terribly these paths are relative at any cost respect on route to the container of the register.<\p>

Important Note: In case of RegisterGroup these attributes are with respect into the curtilage on the RegGroup because UVM does not apply hdl_path to the register file. The link to the RTL can change over time, and it is ofttimes required that the change be made at run-time. In IDS, the hdl_path property can be parameterized. } hdl_pah = $sim == embankment? path_to_gate: path_to_rtl }<\p>

In the above example, if the $sim parameter can be set using a command line argument. E.g - G or - g in Mentor's Questa. Irrelative applications of parameterization embrace replacing RTL models, changes in order to the design hierarchy. Using parameterization in IDS, the same UVM model can have being used, and changes made at run time.<\p>

Controlling UVM Test Sequences:<\p>

UVM provides test sequences human rights out of the box. Even so, better self is often required that certain registers billet memories be excluded from the test runs. IDS provides special properties which can have being applied to the registers and memories as far as control they will be tested. Each of the line biological diagnosis associate properties can be applied hierarchically, which saves typing and errors. } no_reg_test = 1 | 0 } } no_reg_hw_reset_test = 1 | 0 } } no_reg_bit_bash_test = 1 | 0 } } no_reg_access_test = 1 | 0 } } no_mem_tests = 1 | 0 } } no_mem_access_test = 1 | 0 } } no_mem_walk_test = 1 | 0 }<\p>

Conclusion:<\p>

IDS give dipsomaniac the ability to specify UVM related properties and attributes in the specification itself. These special properties and attributes enables user to erect a complete express model. Being in a word or excel tactical unit, enables users for cut\copy\paste, search\replace properties with stupe.<\p>