Quantum Surface Code Scaling For IBM Heavy-Hex Systems
Quantum Surfaces Code
The challenging endeavour of developing scalable quantum error correction (QEC) is slowly making progress according to new pioneering research announced by Arian Vezvaee, Cesar Benito, Mario Morford-Oberst, and their colleagues at the University of Southern California and Universidad Autonoma de Madrid. Their study demonstrates a crucial step towards attaining subthreshold scaling of a surface code memory, even when constrained by an unoptimal architecture, by utilising IBM's heavy-hex design.
This significant progress is the outcome of a carefully co-designed approach that blends a ground-breaking surface code embedding mechanism with highly dependable dynamical decoupling (DD) techniques. The validates improved security of quantum information over many error correction cycles and provides a straightforward way to systematically evaluate scalable surface-code performance under realistic, biassed noise scenarios.
Handling Architectures That Are Not Native
Surface codes are a strong candidate for realistic QEC because of their versatility for two-dimensional structures and potential for fault-tolerant computation. However, to effectively apply these codes, physical error rates must be kept to a minimum in order to reach the threshold needed for resilient logical qubits.
The difficulty rises with the use of hardware like IBM's heavy-hex lattice-based superconducting QPUs.
The heavy-hex layout introduces a significant incompatibility compared to QPUs employing a 2D square lattice specifically designed to reflect surface code connectivity. This reduced connectivity often results in significant delays needed to transfer state across non-neighboring qubits. These extra delays result in "idle gaps," which make the qubits more susceptible to noise and seriously hinder attempts to demonstrate subthreshold scaling. To overcome these structural limitations, the researchers carefully collaborated on the control and code embedding methods.
The Solution Co-Designed: Decoupling, Unfolding, and Folding
The team used bridge ancillas in conjunction with a depth-minimizing SWAP-based "fold-unfold" embedding to map the surface code onto the non-native heavy-hex connection. This method cleverly decreases circuit depth by first folding weight-4 stabilisers into weight-2 operators, measuring them with ancilla qubits, and then unfolding them back to their original shape. Furthermore, circuit depth was reduced by doing away with reset gates and employing software to monitor previous measurement outcomes. This greatly lowered the syndrome extraction round and the associated idle errors.
Crucially, this hardware-aware embedding was coupled with robust Dynamical Decoupling (DD). DD is important in this context because it minimises coherence flaws such as ZZ crosstalk and non-Markovian dephasing that accumulate during the specific idle gaps that are specific to the heavy-hex layout. The researchers were able to maximise efficiency by altering sequences such as universally robust (URm) variations to fill in idle spaces based on time.
Measurements confirmed the significance of DD by eliminating the potential for erroneous claims of subthreshold scaling that could arise from comparing scaled codes without DD to smaller codes that benefit from it. Effective DD is essential for achieving true subthreshold performance by reducing noise to a level that the surface code can handle.
Anisotropic Scaling and Evaluation of Performance
The experimental work requires anisotropic scaling on Heron-generation devices to move from a uniform distance 3 code to anisotropic configurations of (3,5) and (5,3). This allowed them to examine how the protection of logical states for up to 10 QEC cycles was affected by expanding the code distance in a single direction (X or Z basis).
Z-basis logical states are better protected when d x increases, while X-basis logical states are better protected when d x increases. This is a significant finding that supports directional error suppression. For example, the (3, 5) code consistently displayed lower logical error probabilities for the condition than the averaged (3, 3) reference code.
However, real global subthreshold scaling remains challenging. The benefit of extending the coding distance for a single error type does not always outweigh the loss of the orthogonal basis caused by the necessary increase in circuit complexity. Therefore, total entanglement fidelity (EF) was often higher for the smaller programs on the main processor, ibm_aachen.
Entanglement Fidelity Metric: A New Standard
To circumvent the limitations of traditional measurements, the team created a rigorous, model-fit-free performance statistic based on Entanglement Fidelity (EF).
Sometimes, conventional approaches rely on quantum computing to calculate a suppression factor that is determined using a single-parameter fit that assumes small logical SPAM errors, stationary (cycle-independent) errors, and unitality (only Pauli errors). The researchers demonstrated that these assumptions are often incorrect for their data on IBM QPUs. The research demonstrated a continuous difference in mistake probabilities for logical eigenstates as an example of non-unital logical noise.
The new EF measure, which is computed directly from the X- and Z-basis logical-error data provided by the decoder, offers per-cycle, SPAM-aware limits on code performance. The faithfulness of the entire logical channel is clearly measured by this measure, which automatically combines all four possible basis states.
The Entanglement Infidelity Ratio, derived from the EF metric, is suggested as the best benchmark since it is fitting-model-free and does not require the assumption of stationarity. It compares each code in its optimal configuration, which is maximised by the presence or omission of DD, in order to ensure accurate evaluation.
Fault-Tolerant Computing's Future
This work offers a simple and practical way to show successful surface code scaling in non-native platforms. The necessary strategy includes:
Lowering circuit depth through connection-considered embedding.
Incorporating robust DD to effectively minimize non-Markovian and coherent error components.
Scaling is assessed using EF-based, SPAM-aware metrics to produce unambiguous results.
Future circuit-level simulations calibrated to the experimental data provide appealing objectives: access to a slightly larger heavy-hex QPU capable of running a (5,5) code and a slight reduction of approximately 30% in the current experimental noise rates would be sufficient for real global subthreshold scaling under the EF metric. These results set clear, device-level objectives that are critical to the future development of fault-tolerant.
