#powerintegrity

At the heart of PCB reverse engineering is connectivity: which pins connect, through what structures, and with what intent.

1) Start with functional partitioning

Before chasing nets:

Identify sub-systems:

power input + protection

DC/DC stages and rails

MCU/FPGA domain

sensors/actuators

comms interfaces (USB, CAN, Ethernet, RS-485, RF)

Mark them on an annotated photo.

This “block map” gives you context: the same topology patterns repeat across products.

2) Build a rail map early

A rail map is a table:

Rail name (e.g., +5V, +3V3, VCORE)

Source component (converter/regulator)

Loads (ICs, connectors)

Sense/feedback network components

Power-tree clarity prevents schematic chaos later.

3) Connectivity capture methods (choose based on complexity)

A. Visual tracing (single/double-layer, sparse boards)

Strong when traces are visible and simple

Use continuity checks to confirm ambiguous jumps

B. Image-based layer alignment (more systematic)

Create aligned top/bottom copper images

Mark vias and through-hole pins

Build a net table from repeated patterns

C. X-ray-assisted inference (multilayer)

Helps infer planes (GND, VCC) and via fanouts

4) Net naming conventions (save your future self)

Adopt consistent net labels:

GND, VIN, VBAT, +5V0, +3V3

interface: USB_D+, CAN_H, CAN_L, SCL, SDA

control: EN_BUCK1, PGOOD_3V3, RESET_N

clocks: XTAL_IN, XTAL_OUT

5) Schematic reconstruction: top-down beats bottom-up

Instead of drawing every passive first:

Place major ICs and connectors

Add power blocks (regulators, inductors, diodes)

Add interfaces (termination networks, ESD)

Add passives around each IC (decoupling, pull-ups, RC filters)

Validate against common reference designs and expected pin functions

6) Validation checks (catch errors before layout)

Every IC power pin has decoupling and correct rail

Ground pins are truly ground

Differential pairs have plausible routing and termination

Feedback networks match regulator topology

Protection devices are oriented correctly