#enhanceddesignandintegration

Quantum Computing Scales with Fused Silica Ion Traps

A fused silica substrate-based multi-layer ion trap with reduced power dissipation and better performance than silicon-based solutions has been developed. This is crucial to building quantum computers. This development addresses key fabrication restrictions, namely manufacturing quality and power consumption, which are crucial for expanding quantum computing system complexity and reliability.

Alpine Quantum Technologies GmbH, the University of Innsbruck, the University of Graz, the Austrian Academy of Sciences, and Infineon Technologies Austria AG researchers participated in this discovery. In “Test and characterisation of multilayer ion traps on fused silica,” they measured electric field noise using a single trapped ion as a sensitive probe and incorporated temperature sensing down to 10 K.

Solving Silicon's Problems

Engineering classic ion traps etched into silicon substrates has been difficult for scaling quantum systems. These classic designs' intrinsic material restrictions increase power dissipation and electric field noise, which lower qubit coherence and quantum operation fidelity.

Silicon's rich spectrum of two-level systems (TLS), higher dielectric loss, poorer CTE match to metallic layers, and opaque near-infrared behaviour add to qubit stability and performance issues. Quantum processors require more driving power because a 40 mm, 50-ohm coplanar-waveguide line on silicon may decline by more than 1 dB under cryogenic temperatures.

Advantages of Fused Silica

A fused silica substrate, which offers several benefits, is a big shift from previous designs. Using fused silica, a highly pure version of amorphous silicon dioxide (SiO₂), reduces power dissipation and improves system efficiency due to lower dielectric loss than silicon. At 5 GHz and room temperature, fused silica has five times less loss tangent than high-resistivity silicon.

Reduced loss requires less driving power, which saves energy in dilute refrigerators where every microwatt counts. Lower dielectric loss in qubit capacitors enhances relaxation time (T₁) by reducing the participation ratio of lossy dielectrics.

The power efficiency and near-zero thermal expansion of fused silica provide dimensional stability. A 25 mm interposer shrinks by 9 µm when cooled from 300 K to 20 mK, reducing bump-bond pitch and TSV diameter limits and the risk of plastic deformation in metallic columns. Without via-to-metal delamination, MIT Lincoln Laboratory reliability studies show beyond 10,000 heat cycles.

Better design and integration

The trap's multi-layer architecture offers complicated electrode geometries for accurate ion confinement and modification, giving qubit interactions additional control through photolithography and etching. Temperature sensors on the substrate of the trap allow accurate monitoring and adjustment of the cryogenic environment to minimise thermal noise and ensure qubit stability. We need precise and stable ion environment control for qubit coherence.

Fused silica's broadband optical transparency makes it ideal for photonic components. At 1310 nm, fused silica may support microwave structures, host waveguides, on-chip interferometers, and superconducting nanowire single-photon detectors; transmission loss is less than 0.01 dB cm⁻¹. This supports the new roadmap for locally driven, optically read qubits to overcome wiring restrictions.

Strong Construction with Through-Glass Vias

Femtosecond laser-drilled through-glass vias (TGVs) represent a significant advancement. The TGVs' low DC resistance (less than 10 mohm) and inductance (less than 20 pH) make them suitable for flux-bias lines or millivolt control signals and enable stacked qubit tiles and supporting densities for million-qubit device topologies.

Metallisation stacks should start with titanium adhesion, then molybdenum, copper, and gold. Post-plating annealing improves adhesion and stress. Surface passivation with AlO₃ atomic layer deposition has been shown to significantly reduce two-level system (TLS) density by 20 times, enhancing performance.

Automated wafer testing speeds fabrication and ensures device stability before assembly. It lays the groundwork for future research. Currently, 150 mm fused silica wafers are available with sub-nanometer surface roughness and a TTV of less than 5 µm. Foundries are reporting bump-bond yields above 99.8% on interposers with 50 µm copper pillars. Enhanced-life experiments show fused silica interposers can withstand radiation hardness up to 1 Mrad and exceed 10⁸ hours under powered RF stress, exceeding telecom standards by two orders of magnitude.

Zukunft und Scalability

These results progress the creation of larger, more reliable, and more scalable ion trap quantum computers. Fusion-silica interposers eliminate die warpage and minimise microwave attenuation on critical control lines by up to 80%. In addition to new electrode designs and control mechanisms, researchers are investigating automated assembly and better lithography to scale up fabrication. We want large, modular quantum processors to address complicated financial modelling, medicinal development, and materials research problems.

To construct dependable quantum computers, computer scientists, physicists, engineers, and materials experts must collaborate. This game-changing technology requires academic-corporate partnerships for development and adoption. Because manipulating qubits and conducting complicated quantum calculations requires trustworthy control mechanisms, classical control systems must be integrated with the quantum processor.

In summary,