Application in the clock technology of the adaptation and proves in the chip design
With the technological rapid development of the semiconductor, the designs of embedded processor and DSP are more and more complicated, it develop, debug, work too becoming important, so the processor platform offers the strong debug system to already become essential a part in the design.
The embedded processor debug system uses the simulator of the hardware to debug software and goal chip and stand up in succession. Pass the canonial computer communication interface (Ethernet, USB, serial port,etc.) between simulator and PC Carry on communication; Passing accord with IEEEll49 between simulator and goal chip. A canonial JTAG (JointTESTActionGroup) The signal carries on data transmission. With the constant promotion of processor and simulator primary frequency, traditional JTAG interface design lacks and matches essential sequence to JTAG signal transmission with it, it is unable to guarantee simulator and goal chip carry on stable and reliable receiving to JTAG signal, so can't meet the requirement for the high-performance embedded system.
Here, propose a kind of bilateral synchronization adaptation clock technology, has realized stably and reliably that matches across the two-way sequence of the clock land JTAG signal between simulator and goal processor, and designed a kind of TCK clock signal to produce algorithms on this basis, thus solve soft debug system / hardware in coordination with the intersection of JTAG and the intersection of signal and sequence marriage problem when being mutual under verification.
A adaptation clock technology
1. A basic conception
Adaptation clock (AdaptiveClocking) It is a kind of signal synchronisation technique, its basic principle comes from the automatic time setting (SelfTimed) in asynchronous circuit design Technology, namely realize the reliable transmission of two different intersystem signals of clock land by similar acknowledgement mechanism, as Fig. l shows.
Sending and receiving system in Fig. l work under each independent clock land, and sample and move ahead simultaneously the asynchronous input signal. Transmitting system (TransmitSystem) On a basis of clock clk_t, to the receiving system (ReceiveSystem) Transmission data data_t. The receiving system produces clk_r after sampling and moving ahead simultaneously the signal clk_t, and feedback to the transmitting system as the answer back signal, the transmitting system receives clk_r signal, thought the receiving system have already finished die Datenannahme or dealt with, all right new clock and data of onward transmission. In addition, if the receiving system needs to the transport data data_r of transmitting system, on a basis of clk_r, the convenient transmitting system adopts the same mechanism to receive.
The clock mechanism of the adaptation usually adopts the multiple synchronizer to realize, is generally formed by several pieces of D flip-flop, as shown in Fig. 2. The synchronizer reaches the clock signal TCK synchronously the kernel clock land. The progression Ns of the synchronizer usually correlates with concrete device, the general value is 3 or 4. TCK_RET output from D flip-flop of last step, as " acknowledgement " of TCK The signal, feedback to the debug system.
The theory maximum value of TCK signal frequency can follow the values of clock rate of kernel and Ns, calculated briefly by the following formula and got:
The clock agreement of the adaptation is a kind of mechanism of controlling TCK speed by target system, the advantage of mechanism can lie in it pairs of all the intersection of signal and transmission delay Take into account, thus the one that has avoided bringing transmission delay has received the data corruption, improve system performance effectively.
Another advantage of the adaptation clock can make the simulator work under the optimal TCK clock rate. If the simulator supports the convertible TCK frequency, but not used the clock technology of the adaptation, users must set up the maximum operating frequency of TCK and stabilize operating frequency by testing.
The third advantage of the adaptation clock is if the chip kernel clock is convertible too, then TCK_RET signal will vary with it while working too, thus guarantee the transmit data can be moved ahead simultaneously and sampled correctly by the simulator at any time.
1. 2 studies the background
The clock technology of the adaptation is used mainly in the on-line simulator of the embedded processor chip (In-CircuitEmulator at present, ICE) ,Abbreviated as the simulator. The simulator can offer real-time debugging and characteristic trimming function of the embedded processor to developer, it accords with IEEE1149 that this system passes. Logic carries on data interchange within interface and chip of a canonial JTAG.
ARM Company adopted the clock technology of the adaptation in the simulator EmbeddedICE-RT of its embedded processor at first. Recently, TI Company adopted the clock technology of the adaptation in the simulator BlackhawkJTAGEmulator of its 0MAP serial embedded processors too. Their adaptation clock is because of flip-flop - inverter law, as shown in Fig. 2. While sampling TCK_RET signal, it is bilateral along the D flip-flop (D-typeFlip-Flop, DFF) to use one ,The frequency is reduced by half when so can avoid TCK that is produced finally.
