#socdesign

A system on a chip or SOC is being increasingly employed in computers and mobile phones nowadays. As these chips are small in size, lightweight and consume less power, they have proved to be a perfect choice for use in computers and mobiles. A mobile phone is a kind of computer which enables users to perform various functions like storing files, communicating, performing calculations, playing games, etc. while on the go.

A system on a chip consists of millions of components like transistors, peripherals, etc.; all placed inside a single chip. When an instruction is given to a computer, it causes the electrical signals to move from one component to the other of the SOC for performing the intended function. The presence of a huge number of components in a SOC renders designing it quite a complex affair as semiconductor designers have to take care of every minute detail of its components and ensure the SOC design conforms to the specification.

Designing various components of a SOC manually, would consume a lot of time and effort of the semiconductor designers and add up to the costs in their chip design and development projects. To enable chip development teams to perform their SOC design related tasks in a fast and efficient manner, some prominent EDA suppliers have come up with innovative and technologically advanced tools. By using them, chip development teams would be able to automate their SOC design related tasks. This would save their time and effort besides enabling them to complete their projects faster. It would help to improve the productivity and profitability of the concerned chip development companies.

Such an automated tool would not only enable the chip development teams to perform their system on a chip design tasks efficiently and in less time, but would also let them perform a comprehensive and fast SOC verification and validation of the created chip design. So they can ensure it has been created by them as per the specification. Also, they can check whether it has been able to meet the customer expectations and requirements. By performing verification and validation of a system on a chip design, they can identify any errors left in it. So these can be corrected at the design stage itself. This would help to avoid the passage of the errors onto the manufacturing phase where removing them would become more costly and time consuming.

When it comes to performing verification of a SOC design, an automated tool would enable the chip designers to auto generate UVM test-bench consisting of monitors, bus agents, drivers, adaptors, predictors, sequences and sequencers. It will cover all the possible input scenarios. So they can complete the verification right at the first time. It would also enable them to achieve easy back-annotation from the test results. So the designers can better track the progress of their verification efforts. Also, they can generate an effective verification report.

Meg Wheatley:

“So much of human behavior is habitual. And behind every habit is a belief – about people, life, the world. If we can know our beliefs, we can then act with greater consciousness about our behaviors.”  

Cheryl Heller:

"On the hard side, it doesn’t provide much of a portfolio. Nothing to enter into design competitions, few samples to put on your website, harder to explain at a cocktail party just what it is that you do. In fact, most of the invisible things you’ll be designing are private and sensitive to CEOs and leaders of all types of organizations. You can’t even talk about them. This can be a tough shift for designers who are loathe to give up the artifacts of their work. Of course it doesn’t mean that you won’t design any artifacts, it only means that they will be the last thing you design, not the first."

"The most important design challenges in the world are the ones we can’t see – until they are upon us."