#instruction execution

In our last post about Von Neumann's architecture (http://skjorrface.blogspot.it/2013/06/step-by-step-instruction-execution-in.html), first one of this series is here (http://skjorrface.blogspot.it/2013/05/von-neumanns-architecture-how-modern.html), we've described what parts are actually involved in the architecture, what registers, which parts of the CPU etc. In this post we're going to show a practical exercise of instruction execution. We want to calculate the value of the following expression: (a + b) * (c + d), reading  a, b, c and d variables from an input device and writing them onto an output device. A general, simple algorythm would pass through the following steps:

Read values a, b, c and d from the input device;

sum up values a and b;

save the partial result into memory;

sum up values c and d;

multiply the partial result just calculated (c + d) by the previous memorized partial result (a + b);

Write final result onto the output device and show it;

Stop the program execution.

This program requires the use of memory cells, that are normally reserved for programs. Let's suppose these cells are 16, 17, 18 and 19 and that they're respectively reserved for values a, b, c and d and that also cell 20 is available. Von Neumann machine will be able to solve this problem using this specific algorythm (an extension of the above algorythm):

Put into central memory, into cell number 16 (reserved for a), the value read from the input device (this value is available in the Peripherical Command Register [PDR]): do the same for b, c and d, put them into cells 17, 18 and 19;

sum up a and b;

copy the content of cell number 16, matching "a" to register A (A is a CPU register used for calculations);

copy the content of cell number 17, matching "b" to register B (B is another CPU register used for calculations);

sum up the values of these two registers (this is made by ALU);

store the temporary result to cell 20;

sum up c and d;

copy the content of cell number 18, matching "c" to register A;

copy the content of cell number 18, matching "d" to register B;

sum up the contents of these two registers (made again by ALU);

execute multiplication of (a + b) by (c + d);

copy the content of cell 20 to register B, containing the partial result of "a + b";

multiply the content of register A (which still contains the value "b + c" by the content of register B ("a + b);

write the result to the output device and show it;

Stop the program execution.

In our last post (http://skjorrface.blogspot.it/2013/05/von-neumanns-architecture-how-modern.html) we've showed and described a modern computer model, Von Neumann's architecture. We've analyzed every single component, CPU, RAM, Input/Output devices and system bus. In this new post we're going to practically see how a simple computer instruction is processed and executed by the CPU and RAM. To start working the machine needs to load the binary form of a program into the central memory (RAM). The binary form, just like any other kind of information inside a computer, is a sequence of binary words (a sequence of binary digits, 0 or 1). Once loaded into the RAM the CPU can finally execute them using a mechanism we're going to describe later on. It is remarkable that every program is divided into two distinct parts: the first part contains encoded instructions that tell CPU what to actually do once loaded, the second part contains data (input, output, temporary and computed data). These two parts are separated by the "halt" instruction, which makes a program stop. Every instruction execution is divided into three phases: fetch phase, interpretation phase and execution phase. Fetch phase, works as follows:

Contents in program counter register (PC, a CPU register), is transferred to the adress register (AR, another CPU register). PC contains information about the next instruction to execute;

A read operation from central memory (RAM) is done: Contents in the memory cell that matches the address contained in the AR is transferred to the data register (DR, always in the CPU), by the system bus;

Information contained in the DR is transferred to the CIR (Current Instruction register, the name of this CPU register is self explanatory);

Value contained in PC is incremented by 1, so that it will contain the adress to the next instruction to execute and the fetch phase can restart with another instruction. P.S. Sometimes PC will be updated with a totally different value, so that sequentiality is broken (branch instructions).